Subtractor Explained

In electronics, a subtractor – a digital circuit that performs subtraction of numbers – can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend (

Xi

), subtrahend (

Yi

), and a borrow in from the previous (less significant) bit order position (

Bi

). The outputs are the difference bit (

Di

) and borrow bit

Bi+1

. The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite

Xi-Yi-Bi

(which can take the values -2, -1, 0, or 1) as the sum

-2Bi+1+Di

.

Di=XYiBi

Bi+1=Xi<(Yi+Bi)

,where ⊕ represents exclusive or.

Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand.

-B=\bar{B}+1

(definition of two's complement notation)

\begin{alignat}{2} A-B&=A+(-B)\\ &=A+\bar{B}+1\\ \end{alignat}

Half subtractor

X

and subtrahend

Y

and two outputs the difference

D

and borrow out

Bout

. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is,

Bout=1

when

X<Y

. Since

X

and

Y

are bits,

Bout=1

if and only if

X=0

and

Y=1

. An important point worth mentioning is that the half subtractor diagram aside implements

X-Y

and not

Y-X

since

Bout

on the diagram is given by

Bout=\overline{X}Y

.This is an important distinction to make since subtraction itself is not commutative, but the difference bit

D

is calculated using an XOR gate which is commutative.The truth table for the half subtractor is:
InputsOutputs
XYDBout
0000
0111
1010
1100

Using the table above and a Karnaugh map, we find the following logic equations for

D

and

Bout

:

D=XY

Bout=\overlineXY

.

Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is:

      X ── XOR ─┬─────── |X-Y|,  is 0 if X equals Y, 1 otherwise
         ┌──┘   └──┐  
      Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise
where lines to the right are outputs and others (from the top, bottom or left) are inputs.

Full subtractor

The full subtractor is a combinational circuit which is used to perform subtraction of three input bits: the minuend

X

, subtrahend

Y

, and borrow in

Bin

. The full subtractor generates two output bits: the difference

D

and borrow out

Bout

.

Bin

is set when the previous digit is borrowed from

X

. Thus,

Bin

is also subtracted from

X

as well as the subtrahend

Y

. Or in symbols:

X-Y-Bin

. Like the half subtractor, the full subtractor generates a borrow out when it needs to borrow from the next digit. Since we are subtracting

Y

and

Bin

from

X

, a borrow out needs to be generated when

X<Y+Bin

. When a borrow out is generated, 2 is added in the current digit. (This is similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.) Therefore,

D=X-Y-Bin+2Bout

.

The truth table for the full subtractor is:

Inputs Outputs
XYBinDBout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Therefore the equation is:

D=XYBin

Bout=\bar{X}Bin+\bar{X}Y+YBin

See also

References

  1. Foundations Of Digital Electronics by Elijah Mwangi
  2. Beltran, A.A., Nones, K., Salanguit, R.L., Santos, J.B., Santos, J.M., & Dizon, K.J. (2021). Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique.

External links