The ModR/M byte is an important part of instruction encoding for the x86 instruction set.
Opcodes in x86 are generally one-byte, though two-byte instructions and prefixes exist. ModR/M is a byte that, if required, follows the opcode and specifies zero, one, or two operands for the instruction.[1]
The format is:
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Usage | "Mod" | "Reg" | "R/M" |
The "reg" field, if specifying an operand, encodes the three least-significant bits of a register index. Which register (general purpose, AVX, etc.) depends on the instruction being executed. Instructions which take only one operand typically do not use this field, but instead repurpose the bits as an "opcode extension", allowing eight instructions to share a single opcode byte. In opcode listings, these are specified by following the opcode with a slash and a digit 0-7. For example, the opcode for byte increment is, while for byte decrement it is .
The "mod" field specifies the addressing mode for the register/memory ("r/m") operand. If the "mod" field is 11<sub>2</sub>, the "r/m" field encodes a register in the same manner as the "reg" field. However, if the "mod" field is anything else (00<sub>2</sub>, 01<sub>2</sub>, or 10<sub>2</sub>), the "r/m" field specifies an addressing mode. The interpretation of these five bits differs between 16- and 32-/64-bit addressing modes.
In 16-bit mode, the eight possible values of the "r/m" field specify a base register as follows:[2]
where "disp" is the displacement specified by the "mod" bits.
As a special exception, the combination, which would normally specify, instead specifies a 16-bit address [disp16] with no register base at all. To address, one must use a 1-byte displacement ("disp8") form with a displacement of 0.
This results in the full set of combinations:
| + x86 Mod & R/M encoding, 16-bit mode | R/M | MOD | |||
|---|---|---|---|---|---|
| 00 | 01 | 10 | 11 | ||
| 000 | [BX+SI] | [BX+SI+disp8] | [BX+SI+disp16] | AL / AX | |
| 001 | [BX+DI] | [BX+DI+disp8] | [BX+DI+disp16] | CL / CX | |
| 010 | [BP+SI] | [BP+SI+disp8] | [BP+SI+disp16] | DL / DX | |
| 011 | [BP+DI] | [BP+DI+disp8] | [BP+DI+disp16] | BL / BX | |
| 100 | [SI] | [SI+disp8] | [SI+disp16] | AH / SP | |
| 101 | [DI] | [DI+disp8] | [DI+disp16] | CH / BP | |
| 110 | [disp16] | [BP+disp8] | [BP+disp16] | DH / SI | |
| 111 | [BX] | [BX+disp8] | [BX+disp16] | BH / DI | |
In 32-bit mode, there are many differences. First, the MOD=10 case specifies a 32-bit displacement (disp32). Second, the R/M field specifies only a single base register, using the same encoding as the REG field. There are two exceptions:
| + x86 Mod & R/M encoding, 32-bit mode | R/M | MOD | |||
|---|---|---|---|---|---|
| 00 | 01 | 10 | 11 | ||
| 000 | [EAX] | [EAX+disp8] | [EAX+disp32] | AL / AX / EAX | |
| 001 | [ECX] | [ECX+disp8] | [ECX+disp32] | CL / CX / ECX | |
| 010 | [EDX] | [EDX+disp8] | [EDX+disp32] | DL / DX / EDX | |
| 011 | [EBX] | [EBX+disp8] | [EBX+disp32] | BL / BX / EBX | |
| 100 | [<nowiki/>[[#SIB byte|SIB]]] | [<nowiki/>[[#SIB byte|SIB]]+disp8] | [<nowiki/>[[#SIB byte|SIB]]+disp32] | AH / SP / ESP | |
| 101 | [disp32] | [EBP+disp8] | [EBP+disp32] | CH / BP / EBP | |
| 110 | [ESI] | [ESI+disp8] | [ESI+disp32] | DH / SI / ESI | |
| 111 | [EDI] | [EDI+disp8] | [EDI+disp32] | BH / DI / EDI | |
The SIB byte is an optional post-opcode byte in x86 assembly on the i386 and later, used for complex addressing. If present, it appears immediately after the ModR/M byte, before any displacements.
SIB bytes are formatted similarly to ModR/M bytes, and take the form of (scale * index) + base + displacement, where the SCALE is 1, 2, 4, or 8. BASE and INDEX each encode a register.[3] The displacement is a constant offset, whose size is given by the MOD field as usual, which encoded after the SIB byte and added to the final address.[4]
A REX prefix allows the SIB byte to use 16 integer registers.
The general format is as follows:
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Usage | SCALE | INDEX | BASE | |||||
There are, however, two exceptions:
In 64-bit mode, MOD=00 R/M=101 is reassigned to encode relative addresses [RIP+disp32], so an absolute address [disp32] must be encoded using a SIB byte with both of these exceptions.
For most instructions that accept a ModR/M byte, encodings with the SIB byte will result in the computation of a single effective address as as described above. However, some newer x86 instruction set extensions have added instructions that use the SIB byte in other, more specialized ways:
VGATHER* instructions introduced with AVX2 and the VSCATTER* instructions introduced with AVX-512.BNDLDX and BNDSTX.TILELOADD, TILELOADDT1 and TILESTORED.For all the instructions that use VSIB, MIB or SIBMEM addressing, the SIB byte is mandatory - instruction encodings without the SIB byte will cause #UD (invalid instruction exception). For VSIB addressing, the INDEX=100 case is not treated specially (it will cause xmm4/ymm4/zmm4 to be used as index register); other than that, the INDEX=100 and the (MOD=00 BASE=101) special-cases work for VSIB/MIB/SIBMEM addressing in the same way as for regular SIB addressing.
AMD's 64-bit extension to the original instruction set make relatively few changes to 32-bit addressing, with the most significant being that in long mode, 64-bit addressing is the default. 64-bit registers (RAX, RBX, RCX, etc.) are used rather than 32-bit registers for address computation. The displacement is not widened to 64 bits; MOD=11 continues to specify a 32-bit displacement, which is sign-extended to 64 bits.
This may be changed with the address size override prefix, which changes to 32-bit addressing for the following instruction.
A second major addition is the REX prefix.[5] In long mode, opcodes whose highest four bits are 0100 (decimal 4) are a REX prefix, which provide an additional bit for each register field of the following instruction, doubling the number of available processor registers from eight to sixteen. Specifically, the four low-order bits are:
There is one additional effect of a REX prefix: a REX prefix changes how byte registers are addressed. Without a prefix, the available byte registers are AL/CL/DL/BL, then AH/CH/DH/BH. When a REX prefix is present, even a REX prefix of, byte instructions consistently address the low byte of the corresponding word registers, so the available byte become AL/CL/DL/BL/SPL/BPL/SIL/DIL.
The third significant change is RIP-relative addressing. The MOD=00 R/M=101 encoding, which specifies a disp32 address (with no base register) in 32-bit mode, specifies [RIP+disp32] in long mode. With an address-size override prefix, this becomes [EIP+disp32]. The absolute [disp32] mode may be obtained by using MOD=00 R/M=100 to force use of a SIB byte, followed by a SIB byte with BASE=101 and INDEX=100.
For the special-case addressing encodings R/M=100 (to force a SIB byte), MOD=00 R/M=101 (substitute RIP+disp32), and MOD=00 R/M=100 BASE=101 (substitute disp32), the REX.B prefix is not considered. These special-case encodings apply to registers R12 (binary 1100) and R13 (binary 1101) as well, and the same slightly-longer encodings must be used. This is because these exceptions change the encoded instruction size, so must be decoded very quickly so that the following instruction may be located.
The special case where INDEX=100 suppresses the index register (scaling RSP is forbidden), however, does respect the REX.X bit; it is possible to scale R12. This is for two reasons: