LowRISC explained

Logo Alt:Red icon of circuit board traces next to the text lowRISC
lowRISC C.I.C.
Type:Community Interest Company
Founded: in Cambridge, UK
Founders:Gavin Ferris, Alex Bradbury, Robert Mullins
Hq Location City:Cambridge
Hq Location Country:United Kingdom
Products:Ibex, OpenTitan

lowRISC C.I.C. is a not-for-profit company headquartered in Cambridge, UK. It uses collaborative engineering to develop and maintain open source silicon designs and tools.[1] lowRISC is active in RISC-V-related open source hardware and software development and stewards the OpenTitan project.

Projects

OpenTitan

OpenTitan is the first open source silicon Root of Trust (RoT) project.[2] It is designed to be integrated into data center servers, storage devices, peripherals and other hardware.[3] OpenTitan is under the stewardship of lowRISC and collaboratively developed by Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital.[4] The OpenTitan source code is available on GitHub, released under the permissive Apache 2 license.

Ibex CPU core

Ibex is an embedded open source 32-bit in-order RISC-V CPU core, which has been taped out multiple times.[5] Ibex is used in the OpenTitan chip.Development on Ibex started in 2015 under the name "Zero-riscy" and "Micro-riscy" at the ETH Zurich and University of Bologna, where it was part of the PULP platform. In December 2018 lowRISC took over the development.[6] Luca Benini of the ETH Zurich sits on lowRISC' board.

Prototype 64-bit SoC design

The lowRISC prototype 64-bit SoC design is an open source Linux-capable 64-bit RISC-V SoC design. A first version preview release of the source code was made available in April 2015.[7] Since then features were added, such as support for tagged memory and "minion cores", small CPU cores which are dedicated to I/O tasks.[8] The latest version 0.6 was released in November 2018,[9] and is available to download and try out on an FPGA.

Other projects

lowRISC initiated and led the upstreaming of the RISC-V LLVM backend, where Alex Bradbury is code owner.[10]

Governance

Board of directors

Additionally, Mark Hayter of Google sits on the board as an observer.

History

lowRISC was spun out of the University of Cambridge Computer Lab in 2014 by Alex Bradbury, Robert Mullins, and Gavin Ferris with the goal of creating a fully open source SoC and low-cost development board.[11] [12]

In 2015 lowRISC became one of the founding members of the RISC-V Foundation (today: RISC-V International).[13]

Since 2018 lowRISC has been focusing on collaborative engineering with partner organizations. In 2019 the OpenTitan project, stewarded by lowRISC, was announced.[14]

References

  1. Web site: About lowRISC . lowrisc.org . 24 March 2021.
  2. News: Anderson . Tim . Cambridge boffins and Google unveil open-source OpenTitan chip – because you never know who you can trust . 24 March 2021 . The Register . 5 Nov 2019.
  3. Web site: Open source silicon Root of Trust . opentitan.org.
  4. Web site: OpenTitan partners . opentitan.org . 24 March 2021.
  5. Web site: Ibex: An embedded 32 bit RISC-V CPU core . 24 March 2021.
  6. Web site: Ibex Reference Guide: History . 24 March 2021.
  7. Web site: lowRISC tagged memory preview release . lowrisc.org . 24 March 2021 . April 13, 2015.
  8. Web site: Overview of the minion infrastructure . lowrisc.org . 24 March 2021.
  9. Web site: lowRISC 0-6 milestone release . lowrisc.org . 24 March 2021 . 2018-11-12.
  10. Web site: Bradbury . Alex . The RISC-V LLVM backend in Clang/LLVM 9.0 . lowrisc.org . 24 March 2021.
  11. News: Free Core, Some Assembly Required . 24 March 2021 . EETimes . 2016-01-07.
  12. Web site: LowRISC SoC - 1st RISC-V Workshop . YouTube.
  13. Web site: Founding Members . riscv.org . 24 March 2021.
  14. Web site: Bradbury . Alex . Announcing OpenTitan, the First Transparent Silicon Root of Trust . 2019-11-05.