Logical address explained

In computing, a logical address is the address at which an item (memory cell, storage element, network host) appears to reside from the perspective of an executing application program.

A logical address may be different from the physical address due to the operation of an address translator or mapping function. Such mapping functions may be, in the case of a computer memory architecture, a memory management unit (MMU) between the CPU and the memory bus.

There may be more than one level of mapping. For example, on multiprocessor configurations of the IBM S/360, S/370 and successors, IBM distinguishes among

1. Virtual address seen by the program
2. Real address, the result of translating a virtual address
3. Absolute address, the result of mapping a real address using a low-storage prefix^{[1] [2]} assigned to each CPU.

Computer memory

The physical address of computer memory banks may be mapped to different logical addresses for various purposes.

In a system supporting virtual memory, there may actually not be any physical memory mapped to a logical address until an access is attempted. The access triggers special functions of the operating system which reprogram the MMU to map the address to some physical memory, perhaps writing the old contents of that memory to disk and reading back from disk what the memory should contain at the new logical address. In this case, the logical address may be referred to as a virtual address.

See also

• Memory segment
• Flat memory model
• Memory address

Notes and References

1. Book: IBM System/360 Principles of Operation . A22-6821-7 . September 1968 . Eighth . Multisystem Operation . http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=20 . 18 . The relocation procedure applies to the first 4,096 bytes of storage. This area contains all permanent storage assignments and, generally, has special significance to supervisory programs. The relocation is accomplished by inserting a 12-bit prefix in each address which has the high-order 12 bits set to zero and hence, pertains to location 0-4095. . Systems Reference Library . July 21, 2024 .
2. Book: z/Architecture Principles of Operation . SA22-7832-13 . May 2022 . Fourteenth . Prefixing in the z/Architecture Architectural Mode . https://www.vm.ibm.com/library/other/22783213.pdf#page=128 . 3-21–3-23 . Prefixing provides the ability to assign the block of real addresses containing assigned storage locations to a different block in absolute storage for each CPU, thus permitting more than one CPU sharing main storage to operate concurrently with a minimum of interference, especially in the processing of interruptions. . July 21, 2024 .