Load–store architecture explained

In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).^[1]

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.^[1]

For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.^[1]

The earliest example of a load–store architecture was the CDC 6600.^[1] Almost all vector processors (including many GPUs^[2]) use the load–store approach.^[3]

See also

• Load–store unit
• Register–memory architecture

Notes and References

1. Book: Computer architecture: pipelined and parallel processor design . Michael J. Flynn . Michael J. Flynn . 1995 . 0867202041.
2. Web site: AMD GCN reference .
3. Book: Memory systems and pipelined processors . Harvey G. Cragon . Harvey Cragon . 1996 . 0867204745 . 512–513.