| JFET | |
| Type: | Active |
| Pins: | drain, gate, source |
The junction field-effect transistor (JFET) is one of the simplest types of field-effect transistor.[1] JFETs are three-terminal semiconductor devices that can be used as electronically controlled switches or resistors, or to build amplifiers.
Unlike bipolar junction transistors, JFETs are exclusively voltage-controlled in that they do not need a biasing current. Electric charge flows through a semiconducting channel between source and drain terminals. By applying a reverse bias voltage to a gate terminal, the channel is pinched, so that the electric current is impeded or switched off completely. A JFET is usually conducting when there is zero voltage between its gate and source terminals. If a potential difference of the proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current flow, which means less current would flow in the channel between the source and drain terminals.
JFETs are sometimes referred to as depletion-mode devices, as they rely on the principle of a depletion region, which is devoid of majority charge carriers. The depletion region has to be closed to enable current to flow.
JFETs can have an n-type or p-type channel. In the n-type, if the voltage applied to the gate is negative with respect to the source, the current will be reduced (similarly in the p-type, if the voltage applied to the gate is positive with respect to the source). Because a JFET in a common source or common drain configuration has a large input impedance[2] (sometimes on the order of 1010 ohms), little current is drawn from circuits used as input to the gate.
A succession of FET-like devices was patented by Julius Lilienfeld in the 1920s and 1930s. However, materials science and fabrication technology would require decades of advances before FETs could actually be manufactured.
JFET was first patented by Heinrich Welker in 1945.[3] During the 1940s, researchers John Bardeen, Walter Houser Brattain, and William Shockley were trying to build a FET, but failed in their repeated attempts. They discovered the point-contact transistor in the course of trying to diagnose the reasons for their failures. Following Shockley's theoretical treatment on JFET in 1952, a working practical JFET was made in 1953 by George C. Dacey and Ian M. Ross. Japanese engineers Jun-ichi Nishizawa and Y. Watanabe applied for a patent for a similar device in 1950 termed static induction transistor (SIT). The SIT is a type of JFET with a short channel.[4]
High-speed, high-voltage switching with JFETs became technically feasible following the commercial introduction of Silicon carbide (SiC) wide-bandgap devices in 2008. Due to early difficulties in manufacturing - in particular, inconsistencies and low yield - SiC JFETs remained a niche product at first, with correspondingly high costs. By 2018, these manufacturing issues had been mostly resolved. By then, SiC JFETs were also commonly used in conjunction with conventional low-voltage Silicon MOSFETs.[5] In this combination, SiC JFET + Si MOSFET devices have the advantages of wide band-gap devices as well as the easy gate drive of MOSFETs.
The JFET is a long channel of semiconductor material, doped to contain an abundance of positive charge carriers or holes (p-type), or of negative carriers or electrons (n-type). Ohmic contacts at each end form the source (S) and the drain (D). A pn-junction is formed on one or both sides of the channel, or surrounding it using a region with doping opposite to that of the channel, and biased using an ohmic gate contact (G).
JFET operation can be compared to that of a garden hose. The flow of water through a hose can be controlled by squeezing it to reduce the cross section and the flow of electric charge through a JFET is controlled by constricting the current-carrying channel. The current also depends on the electric field between source and drain (analogous to the difference in pressure on either end of the hose). This current dependency is not supported by the characteristics shown in the diagram above a certain applied voltage. This is the saturation region, and the JFET is normally operated in this constant-current region where device current is virtually unaffected by drain-source voltage. The JFET shares this constant-current characteristic with junction transistors and with thermionic tube (valve) tetrodes and pentodes.
Constriction of the conducting channel is accomplished using the field effect: a voltage between the gate and the source is applied to reverse bias the gate-source pn-junction, thereby widening the depletion layer of this junction (see top figure), encroaching upon the conducting channel and restricting its cross-sectional area. The depletion layer is so-called because it is depleted of mobile carriers and so is electrically non-conducting for practical purposes.[6]
When the depletion layer spans the width of the conduction channel, pinch-off is achieved and drain-to-source conduction stops. Pinch-off occurs at a particular reverse bias (VGS) of the gate–source junction. The pinch-off voltage (Vp) (also known as threshold voltage[7] [8] or cut-off voltage[9] [10] [11]) varies considerably, even among devices of the same type. For example, VGS(off) for the Temic J202 device varies from to .[12] Typical values vary from to . (Confusingly, the term pinch-off voltage is also used to refer to the VDS value that separates the linear and saturation regions.)
To switch off an n-channel device requires a negative gate–source voltage (VGS). Conversely, to switch off a p-channel device requires positive VGS.
In normal operation, the electric field developed by the gate blocks source–drain conduction to some extent.
Some JFET devices are symmetrical with respect to the source and drain.
The JFET gate is sometimes drawn in the middle of the channel (instead of at the drain or source electrode as in these examples). This symmetry suggests that "drain" and "source" are interchangeable, so the symbol should be used only for those JFETs where they are indeed interchangeable.
The symbol may be drawn inside a circle (representing the envelope of a discrete device) if the enclosure is important to circuit function, such as dual matched components in the same package.[13]
In every case the arrow head shows the polarity of the P–N junction formed between the channel and the gate. As with an ordinary diode, the arrow points from P to N, the direction of conventional current when forward-biased. An English mnemonic is that the arrow of an N-channel device "points in".
At room temperature, JFET gate current (the reverse leakage of the gate-to-channel junction) is comparable to that of a MOSFET (which has insulating oxide between gate and channel), but much less than the base current of a bipolar junction transistor. The JFET has higher gain (transconductance) than the MOSFET, as well as lower flicker noise, and is therefore used in some low-noise, high input-impedance op-amps. Additionally the JFET is less susceptible to damage from static charge buildup.[14]
qNd\mun
ID=
| bW | |
| L |
qNd\munVDS,
ID = drain–source current,
b = channel thickness for a given gate voltage,
W = channel width,
L = channel length,
q = electron charge = 1.6 C,
μn = electron mobility,
Nd = n-type doping (donor) concentration,
VP = pinch-off voltage.
Then the drain current in the linear region can be approximated as
ID=
| bW | |
| L |
qNd\munVDS=
| aW | |
| L |
qNd\mun\left(1-\sqrt{
| VGS | |
| VP |
In terms of
IDSS
ID=
| 2IDSS | ||||||
|
\left(VGS-VP-
| VDS | |
| 2 |
\right)VDS.
The drain current in the saturation or active[17] or pinch-off region[18] is often approximated in terms of gate bias as[16]
IDS=IDSS\left(1-
| VGS | |
| VP |
\right)2,
where IDSS is the saturation current at zero gate–source voltage, i.e. the maximum current that can flow through the FET from drain to source at any (permissible) drain-to-source voltage (see, e. g., the I–V characteristics diagram above).
In the saturation region, the JFET drain current is most significantly affected by the gate–source voltage and barely affected by the drain–source voltage.
If the channel doping is uniform, such that the depletion region thickness will grow in proportion to the square root of the absolute value of the gate–source voltage, then the channel thickness b can be expressed in terms of the zero-bias channel thickness a as[19]
b=a\left(1-\sqrt{
| VGS | |
| VP |
where
VP is the pinch-off voltage the gate–source voltage at which the channel thickness goes to zero,
a is the channel thickness at zero gate–source voltage.
The transconductance for the junction FET is given by
gm=
| 2IDSS | |
| |VP| |
\left(1-
| VGS | |
| VP |
\right),
where
VP
gfs
yfs
Vds