The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor to determine the memory addresses of the handlers to be executed on interrupts and exceptions.
The details in the description below apply specifically to the x86 architecture. Other architectures have similar data structures, but may behave differently.
The IDT consists of 256 interrupt vectors and the use of the IDT is triggered by three types of events: processor exceptions, hardware interrupts, and software interrupts, which together are referred to as interrupts:
In real mode, the interrupt table is called IVT (interrupt vector table). Up to the 80286, the IVT always resided at the same location in memory, ranging from 0x0000 to 0x03ff, and consisted of 256 far pointers. Hardware interrupts may be mapped to any of the vectors by way of a programmable interrupt controller. On the 80286 and later, the size and locations of the IVT can be changed in the same way as it is done with the IDT (Interrupt descriptor table) in protected mode (i.e., via the LIDT (Load Interrupt Descriptor Table Register) instruction) though it does not change the format of it.[3]
See main article: BIOS interrupt call. The BIOS provides simple real-mode access to a subset of hardware facilities by registering interrupt handlers. They are invoked as software interrupts with the INT assembly instruction and the parameters are passed via registers. These interrupts are used for various tasks like detectingthe system memory layout, configuring VGA output and modes, and accessing the disk early in the boot process.
The IDT is an array of descriptors stored consecutively in memory and indexed by the vector number. It is not necessary to use all of the possible entries: it is sufficient to populate the table up to the highest interrupt vector used, and set the IDT length portion of the accordingly.
The IDTR register is used to store both the linear base address and the limit (length in bytes minus 1) of the IDT. When an interrupt occurs, the processor multiplies the interrupt vector by the entry size (8 for protected mode, 16 for long mode) and adds the result to the IDT base address.[4] If the address is inside the table, the DPL is checked and the interrupt is handled based on the gate type.
The descriptors may be either interrupt gates, trap gates or, for 32-bit protected mode only, task gates. Interrupt and trap gates point to a memory location containing code to execute by specifying both a segment (present in either the GDT or LDT) and an offset within that segment. The only difference between trap and interrupt gates is that interrupt gates will disable further processor handling of maskable hardware interrupts, making them suitable to handle hardware-generated interrupts (conversely, trap gates are useful for handling software interrupts and exceptions). A task gate will cause the currently active task-state segment to be switched, using the hardware task switch mechanism to effectively hand over use of the processor to another program, thread or process.
All INT_NUM between 0x0 and 0x1F, inclusive, are reserved for exceptions by Intel.[5] INT_NUM bigger than 0x1F are to be used for interrupt routines.
| INT_NUM | Event Type | Short Description | |
|---|---|---|---|
| 0x00 | Processor Exception | Division by zero | |
| 0x01 | Processor Exception | Single-step interrupt (see trap flag) | |
| 0x02 | Processor Exception | NMI | |
| 0x03 | Processor Exception | Breakpoint (which benefits from the shorter 0xCC encoding of INT 3) | |
| 0x04 | Processor Exception | Overflow | |
| 0x05 | Processor Exception | Bound Range Exceeded | |
| 0x06 | Processor Exception | Invalid Opcode | |
| 0x07 | Processor Exception | Coprocessor not available | |
| 0x08 | Processor Exception | Double Fault | |
| 0x09 | Processor Exception | Coprocessor Segment Overrun (386 or earlier only) | |
| 0x0A | Processor Exception | Invalid Task State Segment | |
| 0x0B | Processor Exception | Segment not present | |
| 0x0C | Processor Exception | Stack Segment Fault | |
| 0x0D | Processor Exception | General Protection Fault | |
| 0x0E | Processor Exception | Page Fault | |
| 0x0F | Processor Exception | reserved | |
| 0x10 | Processor Exception | x87 Floating Point Exception | |
| 0x11 | Processor Exception | Alignment Check | |
| 0x12 | Processor Exception | Machine Check | |
| 0x13 | Processor Exception | SIMD Floating-Point Exception | |
| 0x14 | Processor Exception | Virtualization Exception | |
| 0x15 | Processor Exception | Control Protection Exception (only available with CET) | |
| 0x16-0x1F | Processor Exception | reserved | |
| 0x20-0x27 | Hardware Interrupt | IRQ 0-7 | |
| 0x70-0x77 | Hardware Interrupt | IRQ 8-15 |
The IBM PC (BIOS and MS-DOS runtime) does not follow the official Intel layout beyond the first five exception vectors implemented in the original 8086. Interrupt 5 is already used for handling the Print Screen key, IRQ 0-7 is mapped to INT_NUM 0x08-0x0F, and BIOS is using most of the vectors in the 0x10-0x1F range as part of its API.[6]
Some Windows programs hook calls to the IDT. This involves writing a kernel mode driver that intercepts calls to the IDT and adds in its own processing. This has never been officially supported by Microsoft, but was not programmatically prevented on its operating systems until 64-bit versions of Windows, where a driver that attempts to use a kernel mode hook will cause the machine to bug check.[7]