Inter-processor interrupt explained

In computing, an inter-processor interrupt (IPI), also known as a shoulder tap, is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system if the interrupting processor requires action from the other processor. Actions that might be requested include:

• flushes of memory management unit caches, such as translation lookaside buffers, on other processors when memory mappings are changed by one processor;
• stopping when the system is being shut down by one processor.
• Notify a processor that higher priority work is available.
• Notify a processor of work that cannot be done on all processors due to, e.g.,
  • asymmetric access to I/O channels^[1]
  • special features on some processors^[2]

Mechanism

The M65MP option of OS/360 used the Direct Control feature of the S/360 to generate an interrupt on another processor; on S/370 and its successors, including z/Architecture, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On IBM PC compatible computers that use the Advanced Programmable Interrupt Controller (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.

Examples

In a multiprocessor system running Microsoft Windows, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:^[3]

1. queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;
2. kernel debugger breakpoint.

IPIs are given an IRQL of 29.^[4]

See also

• Interrupt
• Interrupt handler
• Non-maskable interrupt (NMI)

External links

• Interrupts and Exceptions

Notes and References

1. OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505 . GY28-6616-9 . 271 . Appendix F: Multiprocessing Extensions . http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf#page=282 . Program Logic . . August 28, 2022 .
2. Web site: AMD Technical Information Portal . 2024-07-18 . docs.amd.com.
3. Web site: Inter Processor Interrupt usage . 2024-07-18 . Stack Overflow . en.
4. Web site: Matt . Understanding IRQL . 2014-12-06 . 2002-04-28.