An adder, or summer,[1] is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used in the arithmetic logic units (ALUs). They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.
Although adders can be constructed for many number representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers.In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor.Other signed number representations require more logic around the basic adder.
George Stibitz invented the 2-bit binary adder (the Model K) in 1937.
The half adder adds two single binary digits
A
B
S
C
2C+S
S
C
S
A ⊕ B
C
A ⋅ B
The truth table for the half adder is:
| Inputs | Outputs | ||
|---|---|---|---|
| A | B | Cout | S |
Various half adder digital logic circuits:
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as
A
B
Cin
A
B
Cin
Cout
S
2Cout+S
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. The most common implementation is with:
S=A ⊕ B ⊕ Cin
Cout=(A ⋅ B)+(Cin ⋅ (A ⊕ B))
The above expressions for
S
Cin
In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because when A and B are both 1, the term
(A ⊕ B)
(Cin ⋅ (A ⊕ B))
Due to the functional completeness property of the NAND and NOR gates, a full adder can also be implemented using nine NAND gates, or nine NOR gates.
Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.
A full adder can also be constructed from two half adders by connecting
A
B
S
Cin
S
Cout
S
TFA=2 ⋅ TXOR=2D
The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of:
Tc=TXOR+TAND+TOR=D+D+D=3D
The truth table for the full adder is:
| Inputs | Outputs | |||
|---|---|---|---|---|
| A | B | Cin | Cout | S |
Various full adder digital logic circuits:
It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a
Cin
Cout
Cin=0
The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.The general equation for the worst-case delay for a n-bit carry-ripple adder, accounting for both the sum and carry bits, is:
TCRA(n)=THA+(n-1) ⋅ Tc+Ts=
TFA+(n-1) ⋅ Tc=
3D+(n-1) ⋅ 2D=(2n+1) ⋅ D
A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.[2]
See main article: Carry-lookahead adder.
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders (CLA). They work by creating two signals (
P
G
P
G
P
G
Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry-skip (or carry-bypass) adder which will determine
P
G
By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of lookahead carry units.
Other adder designs include the carry-select adder, conditional sum adder, carry-skip adder, and carry-complete adder.
See main article: Carry-save adder.
If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.
A full adder can be viewed as a 3:2 lossy compressor: it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of (decimal number 2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.
Such compressors can be used to speed up the summation of three or more addends. If the number of addends is exactly three, the layout is known as the carry-save adder. If the number of addends is four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multiplier circuits, which is why these circuits are also known as Dadda and Wallace multipliers.
Using only the Toffoli and CNOT quantum logic gates, it is possible to produce quantum full- and half-adders.[3] [4] [5] The same circuits can also be implemented in classical reversible computation, as both CNOT and Toffoli are also classical logic gates.
Since the quantum Fourier transform have a low circuit complexity, it can efficiently be used for adding numbers as well.[6] [7]
Just as in Binary adders, combining two input currents effectively adds those currents together. Within the constraints of the hardware, non-binary signals (i.e. with a base higher than 2) can be added together to calculate a sum. Also known as a "summing amplifier",[8] this technique can be used to reduce the number of transistors in an addition circuit.