Fin field-effect transistor explained

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal–oxide–semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel (gate all around), forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal–oxide–semiconductor) technology.[1]

FinFET is a type of non-planar transistor, or "3D" transistor.[2] It is the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes.

It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one. The number of fins can be varied to adjust drive strength and performance,[3] with drive strength increasing with a higher number of fins.[4]

History

After the MOSFET was first demonstrated by Mohamed Atalla and Dawon Kahng of Bell Labs in 1960,[5] the concept of a double-gate thin-film transistor (TFT) was proposed by H. R. Farrah (Bendix Corporation) and R. F. Steinberg in 1967.[6] A double-gate MOSFET was later proposed by Toshihiro Sekigawa of the Electrotechnical Laboratory (ETL) in a 1980 patent describing the planar XMOS transistor.[7] Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They demonstrated that short-channel effects can be significantly reduced by sandwiching a fully depleted silicon-on-insulator (SOI) device between two gate electrodes connected together.[8] [9]

The first FinFET transistor type was called a "Depleted Lean-channel Transistor" (DELTA) transistor, which was first fabricated in Japan by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[8] [10] [11] The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.

Indonesian engineer Effendi Leobandung, while working at the University of Minnesota, published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width.[12] This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins.[13] [14] The device had a 35 nm channel width and 70 nm channel length.[12]

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at the University of California, Berkeley to develop a deep sub-micron transistor based on DELTA technology.[15] The group was led by Hisamoto along with TSMC's Chenming Hu. The team made the following breakthroughs between 1998 and 2004.[16]

They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper,[21] used to describe a non-planar, double-gate transistor built on an SOI substrate.[22]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology.[23] In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[24]

In 2020, Chenming Hu received the IEEE Medal of Honor award for his development of the FinFET, which the Institute of Electrical and Electronics Engineers (IEEE) credited with taking transistors to the third dimension and extending Moore's law.[25]

Commercialization

The industry's first 25 nanometer transistor operating on just 0.7 volts was demonstrated in December 2002 by TSMC. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90nm Bulk FinFET process.[16]

In 2011, Intel demonstrated tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.[26] [27] [28]

Commercially produced chips at 22 nm and below have generally utilised FinFET gate designs (but planar processes do exist down to 18 nm, with 12 nm in development). Intel's tri-gate variant were announced at 22 nm in 2011 for its Ivy Bridge microarchitecture.[29] These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries) utilised FinFET designs.

In 2013, SK Hynix began commercial mass-production of a 16nm process,[30] TSMC began production of a 16nm FinFET process,[31] and Samsung Electronics began production of a 10nm process.[32] TSMC began production of a 7 nm process in 2017,[33] and Samsung began production of a 5 nm process in 2018.[34] In 2019, Samsung announced plans for the commercial production of a 3nm GAAFET process by 2021. FD-SOI (Fully Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.[35]

Commercial production of nanoelectronic FinFET semiconductor memory began in the 2010s.[1] In 2013, SK Hynix began mass-production of 16nm NAND flash memory,[30] and Samsung Electronics began production of 10nm multi-level cell (MLC) NAND flash memory.[32] In 2017, TSMC began production of SRAM memory using a 7 nm process.[33]

See also

External links

Notes and References

  1. 10.25103/jestr.151.14. 1791-2377. 15. 1. 110–115. Kamal. Kamal Y.. The Silicon Age: Trends in Semiconductor Devices Industry. Journal of Engineering Science and Technology Review. 2022-05-26. 2022. 249074588.
  2. Web site: What is Finfet? . Computer Hope . 4 July 2019 . April 26, 2017.
  3. Web site: Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011. Anand Lal. Shimpi. AnandTech. 4 May 2011. 18 January 2022.
  4. Web site: VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm . 25 February 2024 .
  5. Web site: 1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated . The Silicon Engine . . 25 September 2019.
  6. H. R. . Farrah . R. F. . Steinberg . Analysis of double-gate thin-film transistor . IEEE Transactions on Electron Devices . February 1967 . 14 . 2 . 69–74 . 10.1109/T-ED.1967.15901 . 1967ITED...14...69F.
  7. Hanpei . Koike . Tadashi . Nakagawa . Toshiro . Sekigawa . E. . Suzuki . Toshiyuki . Tsutsumi . 189033174 . Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode . TechConnect Briefs . 23 February 2003 . 2 . 2003 . 330–333 .
  8. Book: Colinge . J. P. . FinFETs and Other Multi-Gate Transistors . 2008 . Springer Science & Business Media . 9780387717517 . 11 & 39 .
  9. Sekigawa . Toshihiro . Hayashi . Yutaka . Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate . Solid-State Electronics . August 1984 . 27 . 8 . 827–828 . 10.1016/0038-1101(84)90036-4 . 1984SSEle..27..827S . 0038-1101.
  10. Book: Hisamoto . Digh . Kaga . Toru . Kawamoto . Yoshifumi . Takeda . Eiji . International Technical Digest on Electron Devices Meeting . A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET . December 1989 . 833–836 . 10.1109/IEDM.1989.74182. 114072236 .
  11. Web site: IEEE Andrew S. Grove Award Recipients . https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html . dead . September 9, 2018 . . . 4 July 2019.
  12. Book: Leobandung . Effendi . Chou . Stephen Y. . 1996 54th Annual Device Research Conference Digest . Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length . 1996 . 110–111 . 10.1109/DRC.1996.546334. 0-7803-3358-6 . 30066882 .
  13. Leobandung . Effendi . Nanoscale MOSFETs and single charge transistors on SOI . June 1996 . University of Minnesota . Ph.D. thesis . Minneapolis, Minnesota . 72.
  14. Leobandung . Effendi . Gu . Jian . Guo . Lingjie . Chou . Stephen Y. . 1997-11-01 . Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects . Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena . 15 . 6 . 2791–2794 . 10.1116/1.589729 . 1997JVSTB..15.2791L . 1071-1023.
  15. Web site: The Breakthrough Advantage for FPGAs with Tri-Gate Technology . . 2014 . 4 July 2019.
  16. Web site: Tsu-Jae King . Liu . Tsu-Jae King Liu . FinFET: History, Fundamentals and Future . . Symposium on VLSI Technology Short Course . June 11, 2012 . 9 July 2019 . https://web.archive.org/web/20160528220227/http://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse . 28 May 2016 . live .
  17. Book: Hisamoto . Digh . Hu . Chenming . Liu . Tsu-Jae King . Bokor . Jeffrey . Lee . Wen-Chin . Kedzierski . Jakub . Anderson . Erik . Takeuchi . Hideki . Asano . Kazuya . International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) . A folded-channel MOSFET for deep-sub-tenth micron era . December 1998 . 1032–1034 . 10.1109/IEDM.1998.746531. 0-7803-4774-9 . 37774589 .
  18. Book: Hisamoto . Digh . Kedzierski . Jakub . Anderson . Erik . Takeuchi . Hideki . International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) . Sub 50-nm FinFET: PMOS . December 1999 . 67–70 . 10.1109/IEDM.1999.823848 . https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet3.pdf . 0-7803-5410-9 . 7310589 . 2019-09-25 . 2010-06-06 . https://web.archive.org/web/20100606054224/http://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet3.pdf . dead .
  19. Book: Hu . Chenming . Chenming Hu . Choi . Yang-Kyu . Lindert . N. . Xuan . P. . Tang . S. . Ha . D. . Anderson . E. . Bokor . J. . Tsu-Jae King . Liu . International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) . Sub-20 nm CMOS FinFET technologies . December 2001 . 19.1.1–19.1.4 . 10.1109/IEDM.2001.979526. 0-7803-7050-3 . 8908553 .
  20. Book: Ahmed . Shibly . Bell . Scott . Tabery . Cyrus . Bokor . Jeffrey . Kyser . David . Hu . Chenming . Liu . Tsu-Jae King . Yu . Bin . Chang . Leland . Digest. International Electron Devices Meeting . FinFET scaling to 10 nm gate length . December 2002 . 251–254 . 10.1109/IEDM.2002.1175825 . 10.1.1.136.3757 . https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf . 0-7803-7462-2 . 7106946 . 2019-09-25 . 2020-05-27 . https://web.archive.org/web/20200527205136/https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf . dead .
  21. Hisamoto . Digh . Chenming . Chenming Hu . Hu . Bokor . J. . Tsu-Jae . King . Anderson . E. . Kuo . Charles . Asano . K. . Takeuchi . H. . Kedzierski . J. . Wen-Chin . Lee . 5 . FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices. December 2000 . 47 . 12 . 2320–2325 . 10.1109/16.887014 . 10.1.1.211.204 . 2000ITED...47.2320H .
  22. Digh. Hisamoto. Chenming. Hu. Chenming Hu. Xuejue. Huang. Wen-Chin . Lee. Charles. Kuo. Leland. Chang. J.. Kedzierski. E.. Anderson. H.. Takeuchi. Yang-Kyu . Choi. K.. Asano. V.. Subramanian. Tsu-Jae . King. J.. Bokor . 5 . Sub-50 nm P-channel FinFET . IEEE Transactions on Electron Devices . May 2001 . 48 . 5 . 880–886 . 10.1109/16.918235. 2001ITED...48..880H.
  23. Book: Lee, Hyunjin . 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers . Sub-5nm All-Around Gate FinFET for Ultimate Scaling . 2006 . 58–59 . 10.1109/VLSIT.2006.1705215 . etal. 978-1-4244-0005-8 . 10203/698 . 26482358 . free .
  24. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 30 . 3 . 337–349 . 10.1109/TCAD.2010.2097310 . 2011 . Rostami . M. . Mohanram . K. . Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits . 1911/72088 . 2225579 . free .
  25. News: How the Father of FinFETs Helped Save Moore's Law: Chenming Hu, the 2020 IEEE Medal of Honor recipient, took transistors into the third dimension . 27 December 2021 . . 21 April 2020 . en.
  26. Web site: Intel's Revolutionary 22 nm Transistor Technology. Bohr. Mark. Mistry. Kaizad. May 2011. intel.com. April 18, 2018.
  27. News: Intel's Tri-Gate transistors: everything you need to know. Grabham. Dan. May 6, 2011. TechRadar. April 19, 2018.
  28. 10.1109/MM.2017.4241347. CMOS Scaling Trends and Beyond. IEEE Micro. 37. 6. 20–29. 2017. Bohr. Mark T.. Young. Ian A.. 6700881. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011..
  29. Web site: Intel 22nm 3-D Tri-Gate Transistor Technology. Intel Newsroom.
  30. Web site: History: 2010s . . 8 July 2019 . 17 May 2021 . https://web.archive.org/web/20210517040328/https://www.skhynix.com/eng/about/history2010.jsp . dead .
  31. Web site: 16/12nm Technology . . 30 June 2019.
  32. News: Samsung Mass Producing 128Gb 3-bit MLC NAND Flash . 21 June 2019 . . 11 April 2013 . 21 June 2019 . https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html . dead .
  33. Web site: 7nm Technology . . 30 June 2019.
  34. Web site: Samsung Completes Development of 5nm EUV Process Technology. Shilov. Anton. www.anandtech.com. 2019-05-31.
  35. Web site: Samsung, GF Ramp FD-SOI . 27 April 2018 .

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