The Zilog Z280 is a 16-bit microprocessor designed by Zilog as an enhancement of the Zilog Z80 architecture and integrating improvements from the abandoned Zilog Z800 project. First introduced in July 1987, the Z280 is considered to be a commercial failure.
The Z280 was fabricated in CMOS,[1] added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It is capable of efficiently handling 32-bit data operations including hardware multiply, divide, and sign extension. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes (four total possible address spaces). Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed (e.g. a 12MHz CPU with a 3 MHz bus). Unlike the Z80 the Z280 uses a multiplexed arrangement for its address and data buses. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others.
The Z280 had many advanced features for its time, most of them never seen again on a Zilog processor:[2]