Z/Architecture Explained

z/Architecture
Designer:	IBM
Bits:	64-bit
Version:	ARCHLVL 2 and ARCHLVL 3 (2008)
Design:	CISC
Type:	Register–Register Register–Memory Memory–Memory
Encoding:	Variable (2, 4 or 6 bytes long)
Branching:	Condition code, indexing, counting
Endianness:	Big
Predecessor:	ESA/390
Gpr:	16× 64-bit
Fpr:	16× 64-bit
Vpr:	32× 128-bit, VR0-VR15 contain FPR0-FPR15
Registers:	Access 16× 32, breaking-event-address register (BEAR) 64-bit, Control 16×64, Floating Point Control 32-bit, Prefix 64 bit, PSW 128-bit

z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000.^[1] Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15 and z16.

z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors back to the 32-bit-data/24-bit-addressing System/360. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode.^[2] However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.

Features

z/Architecture includes almost all of the features of ESA/390, and adds some new features. Among the features of z/Architecture are

A channel subsystem with the architecture introduced by S/370-XA

Branch relative instructions introduced by ESA/390

Trimodal (24/31/64-bit) addresses

16 32-bit access registers (ARs) introduced by ESA/370

16 64-bit general registers (GRs)

16 64-bit control registers (CRs) introduced by System/370

16 64-bit floating-point registers (FPRs)

32 128-bit vector registers (VRs); bits 0-63 of VR0-VR15 contain FPR0-FPR15

1 32-bit floating point control (FPC) register

1 128-bit processor status register (PSW), which includes a 64-bit instruction address

An 8-KiB prefix storage area (PSA)

Cryptographic Facility

IEEE Binary-floating-point instructions added by ESA/390

IEEE Decimal-floating point instructionsFor information on when each feature was introduced, consult Principles of operation.

Registers

IBM z/Architecture registers

General Registers 0-15

Two's complement value
0	<	-- 1 -->	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	<	-- 8 -->	<	-- 9 -->	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31

Two's complement value (continued)
32	<	-- 33 -->	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38-->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	<	-- 50 -->	<	-- 51 -->	<	-- 52 -->	<	-- 53-->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

Access Registers 0-15

ALESN

ALEN

-- 1 -->

-- 2 -->

-- 3 -->

-- 4 -->

-- 5 -->

-- 9 -->

-- 10 -->

-- 11 -->

-- 12 -->

-- 13 -->

-- 14 -->

-- 16 -->16

-- 17 -->

-- 18 -->

-- 19 -->

-- 20 -->

-- 21 -->

-- 22 -->

-- 23 -->

-- 24 -->

-- 25 -->

-- 26 -->

-- 27 -->

-- 28 -->

-- 29 -->

-- 30 -->


Bits	Field	Meaning
0-6		0000000
7	P	Primary 0=use dispatchable-unit access list 1=use primary-space access list
8-15	ALESN	access-list-entry sequence number
16-31	ALEN	access-list-entry number

Breaking-event-address register (BEAR)

See Principles of Operation
0	<	-- 1 -->	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	<	-- 8 -->	<	-- 9 -->	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31
(continued)
32	<	-- 33 -->	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38 -->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	<	-- 50 -->	<	-- 51 -->	<	-- 52 -->	<	-- 53 -->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

Control Registers 0-15

See Principles of Operation or Control Registers
0	<	-- 1 -->	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	<	-- 8 -->	<	-- 9 -->	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31
(continued)
32	<	-- 33 -->	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38 -->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	<	-- 50 -->	<	-- 51 -->	<	-- 52 -->	<	-- 53 -->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

Floating Point Registers (hexadecimal) 0-15

S	Biased exponent							Mantissa
0	1	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	7	8	<	-- 9 -->	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31

Mantissa (continued)
32	<	-- 33 -->	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38 -->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	<	-- 50 -->	<	-- 51 -->	<	-- 52 -->	<	-- 53 -->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

Floating Point Registers (binary, single precision) 0-15

S	Biased exponent								Mantissa
0	1	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	8	9	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31

Floating Point Registers (binary, double precision) 0-15

S	Biased exponent											Mantissa
0	1	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	<	-- 8 -->	<	-- 9 -->	<	-- 10 -->	11	12	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31

Mantissa (continued)
32	<	-- 33 -->	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38 -->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	<	-- 50 -->	<	-- 51 -->	<	-- 52 -->	<	-- 53 -->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

Prefix register

0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0	<	-- 1 -->	<	-- 2 -->	<	-- 3 -->	<	-- 4 -->	<	-- 5 -->	<	-- 6 -->	<	-- 7 -->	<	-- 8 -->	<	-- 9 -->	<	-- 10 -->	<	-- 11 -->	<	-- 12 -->	<	-- 13 -->	<	-- 14 -->	<	-- 15 -->	<	-- 16 -->	<	-- 17 -->	<	-- 18 -->	<	-- 19 -->	<	-- 20 -->	<	-- 21 -->	<	-- 22 -->	<	-- 23 -->	<	-- 24 -->	<	-- 25 -->	<	-- 26 -->	<	-- 27 -->	<	-- 28 -->	<	-- 29 -->	<	-- 30 -->	31
0	Prefix Bits 33-50																		0	n/a
32	33	<	-- 34 -->	<	-- 35 -->	<	-- 36 -->	<	-- 37 -->	<	-- 38 -->	<	-- 39 -->	<	-- 40 -->	<	-- 41 -->	<	-- 42 -->	<	-- 43 -->	<	-- 44 -->	<	-- 45 -->	<	-- 46 -->	<	-- 47 -->	<	-- 48 -->	<	-- 49 -->	50	51	52	<	-- 53 -->	<	-- 54 -->	<	-- 55 -->	<	-- 56 -->	<	-- 57 -->	<	-- 58 -->	<	-- 59 -->	<	-- 60 -->	<	-- 61 -->	<	-- 62 -->	63

z/Architecture long PSW

I
O

E
X

Key

Program
Mask

R
I

E
A

-- 3 -->

-- 9 -->

-- 10 -->

-- 21 -->

-- 22 -->

-- 25 -->

-- 26 -->

-- 27 -->

-- 28 -->

-- 29 -->

B
A

-- 34 -->

-- 35 -->

-- 36 -->

-- 37 -->

-- 38 -->

-- 39 -->

-- 40 -->

-- 41 -->

-- 42 -->

-- 43 -->

-- 44 -->

-- 45 -->

-- 46 -->

-- 47 -->

-- 48 -->

-- 49 -->

-- 50 -->

-- 51 -->

-- 52 -->

-- 53 -->

-- 54 -->

-- 55 -->

-- 56 -->

-- 57 -->

-- 58 -->

-- 59 -->

-- 60 -->

-- 61 -->

-- 62 -->

Instruction Address

-- 65 -->

-- 66 -->

-- 67 -->

-- 68 -->

-- 69 -->

-- 70 -->

-- 71 -->

-- 72 -->

-- 73 -->

-- 74 -->

-- 75 -->

-- 76 -->

-- 77 -->

-- 78 -->

-- 79 -->

-- 80 -->

-- 81 -->

-- 82 -->

-- 83 -->

-- 84 -->

-- 85 -->

-- 86 -->

-- 87 -->

-- 88 -->

-- 89 -->

-- 90 -->

-- 91 -->

-- 92 -->

-- 93 -->

-- 94 -->

Instruction Address (Continued)

-- 97 -->

-- 98 -->

-- 99 -->

-- 100 -->

-- 101 -->

-- 102 -->

-- 103 -->

-- 104 -->

-- 105 -->

-- 106 -->

-- 107 -->

-- 108 -->

-- 109 -->

-- 110 -->

-- 111 -->

-- 112 -->

-- 113 -->

-- 114 -->

-- 115 -->

-- 116 -->

-- 117 -->

-- 118 -->

-- 119 -->

-- 120 -->

-- 121 -->

-- 122 -->

-- 123 -->

-- 124 -->

-- 125 -->

-- 126 -->

127

Bits

Field

Meaning

PER Mask

DAT mode

I/O mask

External Mask

8-11

Key

PSW key

E=0

Must be zero for LPSWE

Machine-check mask

Wait state

Problem state

16-17

Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode

18-19

Condition Code

20-23

! Bit! Meaning
20	Fixed-point overflow
21	Decimal overflow
22	HFP Exponent underflow
23	HFP Significance

Reserved for IBM

Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero

Basic Addressing mode
0=24 or 64; 1=31

64-127

Instruction Address

z/Architecture short PSW

I
O

E
X

Key

Program
Mask

R
I

E
A

-- 3 -->

-- 9 -->

-- 10 -->

-- 21 -->

-- 22 -->

-- 26 -->

-- 27 -->

-- 28 -->

-- 29 -->

B
A

Instruction Address

-- 34 -->

-- 35 -->

-- 36 -->

-- 37 -->

-- 38 -->

-- 39 -->

-- 40 -->

-- 41 -->

-- 42 -->

-- 43 -->

-- 44 -->

-- 45 -->

-- 46 -->

-- 47 -->

-- 48 -->

-- 49 -->

-- 50 -->

-- 51 -->

-- 52 -->

-- 53 -->

-- 54 -->

-- 55 -->

-- 56 -->

-- 57 -->

-- 58 -->

-- 59 -->

-- 60 -->

-- 61 -->

-- 62 -->

Bits

Field

Meaning

PER Mask

DAT mode

I/O mask

External Mask

8-11

Key

PSW key

E=1

Must be one for LPSW

Machine-check mask

Wait state

Problem state

16-17

Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode

18-19

Condition Code

20-23

! Bit! Meaning
20	Fixed-point overflow
21	Decimal overflow
22	HFP Exponent underflow
23	HFP Significance

Reserved for IBM

Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero

Basic Addressing mode
0=24 or 64; 1=31

33-63

Instruction Address

Each processor has these registers

Access registers
Breaking-event-address register (BEAR)
Control registers
Floating point Control (FPC) register
Floating point registers
General registers
Prefix register
Program status word (PSW)
Vector registers

Access registers

Each CPU has 16 32-bit access registers. When a program running in AR mode specifies register 1-15 as a base register or as a register operand containing an address, the CPU uses the associated access register during address translation.

Breaking-event-address register (BEAR)

The 64-bit BEAR} contains the address of the last instruction the broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 . After an Execute of a branch, the BEAR contains the address of the execute, not that of the branch.

Control registers

The 16 64-bit control registers provide controls over and the status of a CPU, except for information included in the PSW. They are an evolutionary enhancement to the control registers on the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

z/Architecture mode control registers! CR !! bits !! Field
0	8	Transactional-execution control
0	9	Transactional-execution program-interruption filtering override
0	10	Clock-comparator sign control
0	13	Cryptography counter controll
0	14	Processor-activity-instrumentation-extension control
0	15	Measurement-counter-extraction-authorization control
0	30	Warning-track subclass mask
0	32	TRACE TOD-clock control
0	33	SSM-suppression
0	34	TOD-clock-sync control
0	35	Low-address-protection control
0	36	Extraction-authority control
0	37	Secondary-space control
0	38	Fetch-protection-override control
0	39	Storage-protection-override control
0	40	Enhanced-DAT-enablement control
0	43	Instruction-execution-protection-enablement control
0	44	ASN-and-LX-reuse control
0	45	AFP-register control
0	46	Vector enablement control
0	48	Malfunction-alert subclass mask
0	48	Malfunction-alert subclass mask
0	49	Emergency-signal subclass mask
0	50	External-call subclass mask
0	52	Clock-comparator subclass mask
	0	53	CPU-timer subclass mask
0	54	Service-signal subclass mask
0	56	Initialized to 1
0	57	Interrupt-key subclass mask
0	58	Measurement-alert subclass mask
0	59	Timing-alert subclass mask
0	61	Crypto control
1	0-51	Primary Address-Space Control Element (ASCE) Primary region-table origin Primary segment-table origin Primary real-space token origin
1	54	Primary subspace-group control
1	55	Primary private-space control
1	56	Primary storage-alteration-event
1	57	Primary space-switch-event control
1	58	Primary real-space control
1	60-61	Primary designation-type control
1	62-63	Primary table length
2	33-57	Dispatchable-unit-control-table origin
2	59	Guarded-storage-facility enablement control
2	61	Transaction diagnostic scope
2	62-63	Transaction diagnostic control
3	0-31	Secondary ASN-second-table-entry instance number
3	32-47	PSW-key mask
3	48-63	Secondary ASN
4	0-31	Primary ASN-second-table-entry instance number
4	32-47	Authorization index
4	48-63	Primary ASN
5	33-57	Primary-ASN-second-table-entry origin
6	32-39	I/O-interruption subclass mask
7	0-51	Secondary Address-Space Control Element (ASCE) Secondary region-table origin Secondary segment-table origin Secondary real-space token origin
7	54	Secondary subspace-group control
7	55	Secondary private-space control
7	56	Secondary storage-alteration-event control
7	58	Secondary real-space control
7	60-61	Secondary designation-type control
7	62-63	Secondary table length
8	16-31	Enhanced-monitor masks
8	32-47	Extended authorization index
8	48-63	Monitor masks
9	32	Successful-branching-event mask
9	33	Instruction-fetching-event mask
9	34	Storage-alteration-event mask
9	35	Storage-key-alteration-event mask
9	36	Store-using-real-address-event mask
9	37	Zero-address-detection-event mask
9	38	Transaction-end event mask
9	39	Instruction-fetching-nullification-event mask
9	40	Branch-address control
9	41	PER-event-suppression control
9	43	Storage-alteration-space control
10	0-63	PER starting address
11	0-63	PER ending address
12	0	Branch-trace control
12	1	Mode-trace control
12	2-61	Trace-entry address
12	62	ASN-trace control
12	63	Explicit-trace control
13	0-51	Home Address-Space Control Element (ASCE) Home region-table origin Home segment-table origin Home real-space token origin
13	55	Home private-space control
13	56	Home storage-alteration-eventl
13	57	Home space-switch-event control
13	58	Secondary real-space control
13	60-61	Home designation-type control
13	62-63	Home table length
14	32	Set to 1
14	33	Set to 1
14	34	Extended save-area control (ESA/390-compatibility modeonly)
14	35	Channel-report-pending subclass mask
14	36	Recovery subclass mask
14	37	Degradation subclass mask
14	38	External-damage subclass mask
14	39	Warning subclass mask
14	42	TOD-clock-control-override control
14	44	ASN-translation control
14	45-63	ASN-first-table origin
15	0-60	Linkage-stack-entry address

Floating point Control (FPC) register

The FPC register contains Interrupt Masks (IM), Status Flags (SF), Data Exception Code (DXC), Decimal Rounding Mode (DRM) and Binary Rounding Mode (BRM). An interruption only stores the DXC if the FPC register if the AFP-register (additional floating-point register) control bit, bit 13 of control register 0, is one. Also, while individual bits of the DXC usually have significance, programs should normally treat it as an 8-bit integer rather than querying individual bits.

FPC fields
Byte name	Bits	Field name	Use
masks	0	IMi	IEEE-invalid-operation mask
masks	1	IMz	IEEE-division-by-zero mask
masks	2	IMo	IEEE-overflow mask
masks	3	IMu	IEEE-underflow mask
masks	4	IMx	IEEE-inexact mask
masks	5	IMq	Quantum-exception mask
flags	8	SFi	IEEE-invalid-operation flag
flags	9	SFz	IEEE-division-by-zero
flags	10	SFo	IEEE-overflow flag
flags	11	SFu	IEEE-underflow flag
flags	12	SFx	IEEE-inexact flag
flags	13	SFq	Quantum-exception flag
DXC	16-23	DXC	Data-exception code
DXC	16	i	IEEE-invalid-operation
DXC	17	z	IEEE-division-by-zero
DXC	18	o	IEEE-overflow
DXC	19	u	IEEE-underflow mask
DXC	20	x	IEEE-inexact mask
DXC	21	y/q	Quantum-exception mask
	25-27	DRM	DFP rounding mode
	29-31	BRM	BFP rounding mode

Floating point registers

Each CPU had 16 64-bit floating point registers; FP0-15 occupy bits 0-63 of VR0-15.

General registers

Each CPU has 16 64-bit general registers, which serve as accumulators, base registers and index registers. Instructions designated as Grandé operate on all 64 bits; some instructions added by the Extended-Immediate Facility operate on any halfword or word in the register; most other instructions do not change or use bits 0-31.

Prefix register

The prefix register is used in translating a real address to an absolute address. In z/Architecture mode, the PSA is 2 pages (8 KiB). Bits 0-32 and 51-63 are always zero. If bits 0-50 of a real address are zero then they are replaced by bits 0-50 of the prefix register; if bits 0-50 of the real address are equal to bits 0-50 of the prefix register then they are replaced with zeros.

Program status word (PSW)

The PSW holds the instruction address and other fields reflecting the status of the program currently running on a CPU. The status of the program is also affected by the contents of the Control registers.

Vector registers

Each CPU has 32 128-bit vector registers.

Notes and References

http://www.cl.cam.ac.uk/teaching/0607/CompArch/ibm-z-plambeck.pdf Development and Attributes of z/Architecture
Web site: Accommodate functions for the z13 server to be discontinued on future servers . . 25 June 2015 . 2017-09-18 . 2017-09-15 . https://web.archive.org/web/20170915023438/https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.e0zm100/z132012hw1.htm . live .