| Yuan Taur | |
| Native Name: | 陶 元 |
| Birth Date: | 27 September 1946 |
| Birth Place: | Jiangxi, China |
| Nationality: | Chinese American |
| Occupation: | Electrical engineer and academic |
| Education: | BS., Physics (1967) PhD., Physics (1974) |
| Alma Mater: | National Taiwan University University of California, Berkeley |
| Workplaces: | University of California, San Diego |
Yuan Taur (Chinese:陶 元) is a Chinese American electrical engineer and an academic. He is a Distinguished Professor of Electrical and Computer Engineering (ECE) at the University of California, San Diego.[1]
Taur is known for his research in semiconductor device design and modeling, focusing on the structure and physics of transistors. He holds 14 U.S. patents and has authored or co-authored over 200 technical papers, in addition to coauthoring Fundamentals of Modern VLSI Devices with Tak Ning, spanning three editions released in 1998, 2009, and 2022.[2]
In 1998, Taur was elected as a Fellow of the IEEE. He served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011.[3] He was the recipient of the IEEE Electron Devices Society's J. J. Ebers Award in 2012 "for contributions to the advancement of several generations of CMOS process technologies,"[4] and received the IEEE Electron Devices Society's Distinguished Service Award in 2014.[5]
In high school, Taur developed a keen interest in mathematics. At the age of 16, he achieved the highest score among all high school graduates in Taiwan's united college entrance exam in 1963. Taur earned his B.S. degree in physics from National Taiwan University in Taipei, Taiwan, in 1967, and came to the US in 1968 to pursue a Ph.D. in physics at the University of California, Berkeley, which he completed in 1974.[6]
From 1979 to 1981, Taur held an appointment at Rockwell International Science Center in Thousand Oaks, California, focusing on II-VI semiconductor devices for infrared sensor applications. Following this, from 1981 to 2001, he served in the Silicon Technology Department at IBM Thomas J. Watson Research Center in Yorktown Heights, New York, holding the position of Manager of Exploratory Devices and Processes. Having joined the Jacobs School of Engineering in 2001, he has since held positions as a professor in the Department of Electrical and Computer Engineering at the University of California, San Diego, and was later appointed as a Distinguished Professor in 2014.[1]
While working at IBM T. J. Watson Research Center during 1981 to 2001, Taur's research focused on scaling CMOS transistors from 1 micron to 100 nm.[7] He investigated issues like avoiding CMOS latch-up, minimizing parasitic series resistance, gate work function for surface-channel pMOS, and shallow trench isolation process for achieving higher packing density. He also reported the first 100 nm CMOS transistors and published a conceptual super-halo design for 25 nm CMOS near the limit of bulk CMOS scaling.[8] In addition, he wrote an article on the limits to CMOS transistor scaling, listing factors like quantum mechanical tunneling through thin insulating layers, short-channel effect, standby power dissipation caused by injection of thermal electrons over a potential barrier.[9]
During his tenure at UCSD from 2001 to 2024, Taur's research has been mainly on the design and modeling of transistors from 100 nm to 10 nm.[2] He contributed to the field by publishing an analytic potential model for symmetric double-gate MOSFETs that remains continuous across all bias regions.[10] Additionally, he and his students published a series of papers on compact modeling of double-gate MOSFETs and nanowire transistors, a distributed model for oxide traps in III-V MOSFETs, and tunneling MOSFETs with a staggered source-channel heterojunction.[11] [12] [13] In 2019, he developed a non-GCA model capable of providing continuous solutions into the MOSFET saturation region, addressing limitations inherent in conventional models.[14]
Taur's textbook, Fundamentals of Modern VLSI Devices, used in first-year graduate courses on microelectronics worldwide, has been translated into Japanese for all three editions and into Chinese for the 2nd and 3rd editions. This work delved into CMOS and bipolar VLSI devices, covering semiconductor physics, design optimization, power consumption, scaling, and physical limitations. The second edition elaborated on device parameter relationships, integrating MOSFET scale length theory, SiGe-base bipolar devices, and silicon-on-insulators, and included a chapter on VLSI memory devices, both volatile and non-volatile. Its third edition, published in 2022, expanded on modern VLSI device properties and designs, introducing about 25% new material on advancements like high-k gate dielectrics, double-gate MOSFETs, lateral bipolar transistors, and non-GCA MOSFET model.[15]