| Vivado Design Suite | |
| Vivado Design Suite | |
| Author: | Xilinx |
| Developer: | AMD |
| Released: | [1] |
| Latest Release Version: | 2023.1.1[2] |
| Latest Release Date: | [3] |
| Programming Language: | C++ |
| Operating System: | Microsoft Windows, Linux |
| Language: | English |
| Genre: | EDA |
| License: | WebPACK Edition: no-cost for selected (smaller) devices[4] Other editions: commercial |
| Website: | https://www.xilinx.com/products/design-tools/vivado.html |
Vivado Design Suite is a software suite for synthesis and analysis of hardware description language (HDL) designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.[1] [5] [6] [7] Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE).[8] [9] [10]
Like the later versions of ISE, Vivado includes the in-built logic simulator.[11] Vivado also introduces high-level synthesis, with a toolchain that converts C code into programmable logic.[6]
Replacing the 15 year old ISE with Vivado Design Suite took 1000 man-years and cost US$200 million.[12]
Vivado was introduced in April 2012,[1] and is an integrated design environment (IDE) with system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.[13] A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.[14]
The Vivado High-Level Synthesis compiler enables C, C++ and SystemC programs to be directly targeted into Xilinx devices without the need to manually create RTL.[15] [16] [17] Vivado HLS is widely reviewed to increase developer productivity, and is confirmed to support C++ classes, templates, functions and operator overloading.[18] [16] Vivado 2014.1 introduced support for automatically converting OpenCL kernels to IP for Xilinx devices.[16] OpenCL kernels are programs that execute across various CPU, GPU and FPGA platforms.[16]
The Vivado Simulator is a component of the Vivado Design Suite. It is a compiled-language simulator that supports mixed-language, Tcl scripts, encrypted IP and enhanced verification.
The Vivado IP Integrator allows engineers to quickly integrate and configure IP from the large Xilinx IP library. The Integrator is also tuned for MathWorks Simulink designs built with Xilinx's System Generator and Vivado High-Level Synthesis.[19]
The Vivado Tcl Store is a scripting system for developing add-ons to Vivado, and can be used to add and modify Vivado's capabilities.[20] Tcl is the scripting language on which Vivado itself is based.[20] All of Vivado's underlying functions can be invoked and controlled via Tcl scripts.[20]
Vivado supports Xilinx's 7-series and all the newer devices (UltraScale and UltraScale+ series).[3] For development targeting older Xilinx's devices and CPLDs, the already discontinued Xilinx ISE has to be used.