| Manuf1: | Western Design Center |
| Slowest: | 1 |
| Slow-Unit: | MHz |
| Fastest: | 14 |
| Fast-Unit: | MHz |
| Predecessor: | MOS Technology 6502 |
The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502. It uses less power than the original 6502, fixes several problems, and adds new instructions. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in portable computer roles and industrial microcontroller systems. The 65C02 has also been used in some home computers, as well as in embedded applications, including medical-grade implanted devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02was officially released sometime shortly after.[1] WDC licensed the design to Synertek, NCR, GTE Microcircuits, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
The 65C02 is a low cost, general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The register set is small, with a single 8-bit accumulator (A), two 8-bit index registers (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" ($0000 to $00FF), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The stack lies in the next 256 bytes, page one ($0100 to $01FF), and cannot be moved or extended. The stack grows backwards with the stack pointer (S) starting at $01FF and decrementing as the stack grows.[2] It has a variable-length instruction set, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and can be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip (SoC) designs.
A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).[3] As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.[4]
The W65C02S–14 is the production version, and is available in PDIP, PLCC and QFP packages. The maximum officially supported Ø2 (primary) clock speed is 14 MHz when operated at 5 volts, indicated by the –14 part number suffix (hobbyists have developed 65C02 homebrew systems that run faster than the official rating). The "S" designation indicates that the part has a fully static core, a feature that allows Ø2 to be slowed down or fully stopped in either the high or low state with no loss of data.[5] Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
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VPB) output indicates when interrupt vectors are being addressedMLB) output indicates to other bus masters when a read-modify-write instruction is being processedWAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external eventsThe W65C02S may be operated at any convenient supply voltage (VDD) between 1.8 and 5 volts (±5%). The data sheet AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it.
The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818 MHz (NTSC colour carrier frequency × 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), etc., as long as VDD is sufficient to support the frequency. Designer Bill Mensch has pointed out that FMAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise FMAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of printed circuit board space.
WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.
Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.
The original 6502 has 56 instructions, which, when combined with different addressing modes, produce a total of 151 opcodes of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes with low-order 4-bits with 3, 7, B or F left entirely unused, the code with low-order 2 having only a single opcode.[6]
On the 6502, some of these leftover codes actually perform computation. Due to the way the 6502's instruction decoder works, simply setting certain bits in the opcode cause parts of the instruction processing to take place. Some of these opcodes immediately crash the processor, while other perform useful functions and were even given unofficial assembler mnemonics by some programmers.[7]
The 65C02 adds new opcodes that use some of these previously undocumented instruction slots. For example, $FF is used for the new BBS instruction. Those which remain truly unused are equivalent to [[NOP (code)|NOP]]s. 6502 programs using those opcodes will not work on the 65C02.
The original 6502 had several errata when initially launched. Early versions of the processor had no ROR (rotate right) instruction and MOS Technology manuals did not document it either. ROR was implemented very early in the production run and the vast majority of machines using the processor support this instruction.[8]
A bug that is present in all NMOS variants of the 6502 involves the jump instruction when using indirect addressing. In this addressing mode, the target address of the JMP instruction is fetched from memory, the jump vector, rather than being an operand to the JMP instruction. For example, JMP ($1234) would fetch the value in memory locations (least significant byte) and (most significant byte) and load those values into the program counter, which would then cause the processor to continue execution at the address stored in the vector.
The bug appears when the vector address ends in, which is the boundary of a memory page. In this case, JMP will fetch the most significant byte of the target address from of the original page rather than of the new page. Hence JMP ($12FF) would get the least significant byte of the target address at and the most significant byte of the target address from rather than . The 65C02 corrected this issue.
More of an oversight than a bug, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a reset or interrupt. This means programmers have to set the flag to a known value in order to avoid any bugs related to arithmetic operations. As a result, one finds a CLD instruction (CLear Decimal) in almost all 6502 interrupt handlers, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode.
During decimal mode arithmetic, the NMOS 6502 will update the (N)egative, o(V)erflow and (Z)ero flags to reflect the result of underlying binary arithmetic, that is, the flags are reflecting a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction.[9]
When executing a read-modify-write (R-M-W) instruction, such as INC ''addr'', all NMOS variants will do a double write on addr, first rewriting the current value found at addr and then writing the modified value. This behavior can result in difficult-to-resolve bugs if addr is a hardware register. This may occur if the hardware is watching for changes to the value in the register and then performs an action, in this case, it will perform two actions, one with the original value and then again with the new value. The 65C02 instead performs a double read of addr, followed by a single write.
When performing indexed addressing, if indexing crosses a page boundary all NMOS variants will read from an invalid address before accessing the correct address. As with a R-M-W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary (which means indexing will never cross into the next page). With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X will do a dummy read on prior to the value of X being added to . Again, if indexing on hardware register addresses, this bug can result in undefined behavior.
If an NMOS 6502 is fetching a BRK (software interrupt) opcode at the same time a hardware interrupt occurs, the BRK will be ignored as the processor reacts to the hardware interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK.
The 6502 has two indirect addressing modes which dereference through 16-bit addresses stored in page zero:
LDA ($10,X), adds the X register to the given page zero address before reading the 16-bit vector. In this example, if X is 5, it reads the 16-bit address from location $15/$16. This is useful when there is an array of pointers in page zero.LDA ($10),Y adds the Y register to the 16-bit vector read from the given page zero address. For instance, if Y is 5, and contains the vector, This reads the value from . This performs pointer-offset addressing.A downside of this model is that if indexing is not needed but the address is in the zero page, one of the index registers must still be set to zero and used in one of these instructions. The 65C02 added a non-indexed indirect addressing mode LDA ($10) to all instructions that used indexed indirect and indirect indexed modes, freeing up the index registers.[10]
The 6502's instruction had a unique (among 6502 instructions) addressing mode known as "absolute indirect" that read a 16-bit value from a given memory address and then jumped to the address in that 16-bit value. For instance, if memory location holds $34 and holds $12, JMP ($A000) would read those two bytes, construct the value, and then jump to that location.
One common use for indirect addressing is to build branch tables, a list of entry points for subroutines that can be accessed using an index. For instance, a device driver might list the entry points for,,, etc in a table at . is the third entry, zero indexed, and each address requires 16-bits, so to call one would use something similar to JMP ($A004). If the driver is updated and the subroutine code moves in memory, any existing code will still work as long as the table of pointers remains at .
The 65C02 added the new "indexed absolute indirect" mode which eased the use of branch tables. This mode added the value of the X register to the absolute address and took the 16-bit address from the resulting location. For instance, to access the function from the table above, one would store 4 in X, then JMP ($A000,X). This style of access makes accessing branch tables simpler as a single base address is used in conjunction with an 8-bit offset.[10] The same could be achieved in the NMOS version using indexed indirect mode, but only if the table was in the zero page, a limited resource. Allowing these to be constructed outside zero page not only lessened the demand for this resource, but also allowed the tables to be constructed in ROM.
In addition to the new addressing modes, the "base model" 65C02 also added a set of new instructions.
INC and DEC with no parameters now increment or decrement the accumulator. This was an odd oversight in the original instruction set, which only included INX/DEX,INY/DEY and INC ''addr''/DEC ''addr''. Some assemblers use the alternate forms INA/DEA or INC A/DEC A.STZ ''addr'', STore Zero in addr. Replaces the need to LDA #0;STA ''addr'' and doesn't require changing the value of the accumulator. As this task is common in most programs, using can reduce code size, both by eliminating the as well as any code needed to save the value of the accumulator, typically a PHA PLA pair.PHX,PLX,PHY,PLY, push and pull the X and Y registers to/from the stack. Previously, only the accumulator and status register had push and pull instructions. X and Y could only be stacked by moving them to the accumulator first with TXA or TYA, thereby changing the accumulator contents, then using PHA.BRA, branch always. Operates like a JMP but uses a 1-byte relative address like other branches, saving a byte. The speed is often the same as the 3 cycle absolute JMP unless a page is crossed which would make the BRA version 1 cycle longer (4 cycles).[11] As the address is relative, it is also useful when writing relocatable code, a common task in the era before memory management units.Both WDC and Rockwell contributed improvements to the bit testing and manipulation functions in the 65C02. WDC added new addressing modes to the BIT instruction that was present in the 6502, as well two new instructions for convenient manipulation of bit fields, a common activity in device drivers.
in the 65C02 adds immediate mode, zero page indexed by X and absolute indexed by X addressing. Immediate mode addressing is particularly convenient in that it is completely non-destructive. For example:
LDA $1234
BIT #%00010000
may be used in place of:
LDA $1234
AND #%00010000
The operation changes the value in the accumulator, so the original value loaded from $1234 is lost. Using leaves the value in the accumulator unchanged, so subsequent code can make additional tests against the original value, avoiding having to re-load the value from memory.
In addition to the enhancements of the instruction, WDC added two instructions designed to conveniently manipulate bit fields:
TSB ''addr'' and TRB ''addr'', Test and Set Bits and Test and Reset Bits.A mask in the accumulator (.A) is logically ANDed with memory at addr, which location may be zero page or absolute. The Z flag in the status register is conditioned according to the result of the logical AND—no other status register flags are affected. Furthermore, bits in addr are set (TSB) or cleared (TRB) according to the mask in .A. TSB performs a logical after the logical and stores the result of the logical at addr, whereas TRB stores the results of the logical at addr. In both cases, the Z flag in the status register indicates the result of .A AND ''addr'' before the content of addr is changed. TRB and TSB thus replace a sequence of instructions, essentially combining the instruction with additional steps to save the computational changes, but in a way that reports the status of the affected value before it is changed.
Rockwell's changes added more bit manipulation instructions for directly setting and testing any bit, and combining the test, clear and branch into a single opcode. The new instructions were available from the start in Rockwell's R65C00 family, but was not part of the original 65C02 specification and not found in versions made by WDC or its other licensees. These were later copied back into the baseline design, and were available in later WDC versions.
Rockwell-specific instructions are:
SMB''bit#'' ''zp'' and RMB''bit#'' ''zp''. Set or Reset (clear) bit number bit# in zero page byte zp.RMB and SMB are used to clear (RMB) or set (SMB) individual bits in a bit field, each replacing a sequence of three instructions. As RMB and SMB are zero page addressing only, these instructions are limited in usefulness and are primarily of value in systems in which device registers are present in zero page. The bit# component of the instruction is often written as part of the mnemonic, such as SMB1 $12 which sets bit 1 in zero-page address $12. Some assemblers treat bit# as part of the instruction's operand, e.g., SMB '''1''',$12, which has the advantage of allowing it to be replaced by a variable name or calculated number.
BBS''bit#'' ''zp'',''addr'' and BBR''bit#'' ''zp'',''addr''. Branch on Bit Set/Reset.The same zero-page addressing and limitations as RMB and SMB apply, but branches to addr if the selected bit of the zero page byte zp is clear (BBR) or set (BBS). As with RMB and SMB above, the bit# component of the instruction is often written as part of the mnemonic, such as BBS1 $12,''addr'' which branches to the address label addr if bit 1 of the byte at zero-page address $12 is set. Some assemblers treat bit# as part of the instruction's operand, e.g., BBS '''1''',$12,''addr'', which has the advantage of allowing it to be replaced by a variable name or calculated number. As is the case with RMB and SMB, BBR and BBS replace a sequence of three instructions.
In addition to the new commands above, WDC also added the STP and WAI instructions for supporting low-power modes.
, STop the Processor, halted all processing until a hardware reset was issued. This could be used to put a system to "sleep" and then rapidly wake it with a reset. Normally this would require some external system to maintain main memory, and it was not widely used.
t had a similar effect, entering low-power mode, but this instruction woke the processor up again on the reception of an interrupt. Previously, handling an interrupt generally involved running a loop to check if an interrupt has been received, sometimes known as "spinning", checking the type when one is received, and then jumping to the processing code. This meant the processor was running during the entire process, even when no interrupts were occurring.
In contrast, in the 65C02, interrupt code could be written by having a followed immediately by a or to the handler. When the was encountered, processing stopped and the processor went into low-power mode. When the interrupt was received, it immediately processed the and handled the request.
This had the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends one cycle to save its location. With, the processor enters the low-power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction and the processor can safely continue without spending a cycle saving state.
The 65SC02 is a variant of the WDC 65C02 without bit instructions.[12] [13]