A test register, in the Intel 80386 and Intel 80486 processor, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. Regular programs don't usually require these registers to work. With the Pentium, the test registers were replaced by a variety of model-specific registers (MSRs).[1]
In the 80386, two test registers, TR6 and TR7, were provided for the purpose of TLB testing. TR6 was the test command register, and TR7 was the test data register. The 80486 provided three additional registers, TR3, TR4 and TR5, for testing of the L1 cache. TR3 was a data register, TR4 was an address register and TR5 was a command register. These registers were accessed by variants of the MOV instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both real-address mode and protected mode. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at privilege level 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on most CPUs newer than 80486.
The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as 0F 26 /r (with r/m being the GPR, and reg being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as 0F 24 /r (with r/m being the GPR, and reg being the test register).[2] Only register-register moves are allowed; memory forms of the ModR/M byte are undefined. In other words, the mod field (the two MSBs) must be set to 1.
The test registers and/or associated opcodes were supported in the following x86 processors:
| Processors | colspan="3" | Cache Test Registers | TLB Test Registers | ||||
|---|---|---|---|---|---|---|---|
| TR0 | TR1 | TR2 | TR3 | TR4 | TR5 | TR6 | TR7 |
| Intel 386 (all models) | colspan="3" | colspan="1" | colspan="2" | colspan="2" | |||
| Intel 486 (all models) | colspan="3" | colspan="3" | colspan="2" | ||||
| AMD 386 (all models) AMD Élan SC3xx | colspan="3" | colspan="2" | colspan="2" | ||||
| AMD 486 (all models) AMD 5x86 AMD Élan SC4xx,SC5xx | colspan="3" | colspan="3" | colspan="2" | ||||
| C&T Super386 | colspan="3" | colspan="3" | colspan="3" | ||||
| NexGen Nx586 | colspan="3" | colspan="3" | colspan="2" | ||||
| colspan="3" | colspan="3" | colspan="2" | |||||
| colspan="2" | colspan="3" | colspan="2" | |||||
| colspan="3" | colspan="3" | colspan="2" | |||||
| colspan="3" | colspan="3" | colspan="2" | |||||
| NatSemi Geode GX2 AMD Geode GX, LX | colspan="8" | ||||||
| IDT WinChip (all models) | colspan="8" | ||||||
| Intel Quark X1000 | colspan="3" | colspan="3" | |||||