Spin-transfer torque explained

Spin-transfer torque (STT) is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be modified using a spin-polarized current.

Charge carriers (such as electrons) have a property known as spin which is a small quantity of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (consisting of 50% spin-up and 50% spin-down electrons); a spin polarized current is one with more electrons of either spin. By passing a current through a thick magnetic layer (usually called the “fixed layer”), one can produce a spin-polarized current. If this spin-polarized current is directed into a second, thinner magnetic layer (the “free layer”), the angular momentum can be transferred to this layer, changing its orientation. This can be used to excite oscillations or even flip the orientation of the magnet. The effects are usually seen only in nanometer scale devices.

Spin-transfer torque memory

Spin-transfer torque can be used to flip the active elements in magnetic random-access memory. Spin-transfer torque magnetic random-access memory (STT-RAM or STT-MRAM) is a non-volatile memory with near-zero leakage power consumption which is a major advantage over charge-based memories such as SRAM and DRAM. STT-RAM also has the advantages of lower power consumption and better scalability than conventional magnetoresistive random-access memory (MRAM) which uses magnetic fields to flip the active elements.[1] Spin-transfer torque technology has the potential to make possible MRAM devices combining low current requirements and reduced cost; however, the amount of current needed to reorient the magnetization is presently too high for most commercial applications, and the reduction of this current density alone is the basis for present academic research in spin electronics.[2]

Industrial development

Sony Research Center published the first Japan Patent application for S.P.I.N.O.R. (Spin Polarized Injection Non-Volatile Orthogonal Read/Write RAM), a forerunner of STT RAM, in 1997.[3] Subsequently, at IEDM 2005, Sony researchers reported the first working 4kb STT memory, dubbed Spin-RAM, with replacement of the paramagnetic spacer layer of SPINOR memory with MgO dielectric.[4]

Hynix Semiconductor and Grandis formed a partnership in April 2008 to explore commercial development of STT-RAM technology.[5] [6]

Hitachi and Tohoku University demonstrated a 32-Mbit STT-RAM in June 2009.[7]

On August 1, 2011, Grandis announced that it had been purchased by Samsung Electronics for an undisclosed sum.[8]

In 2011, Qualcomm presented a 1 Mbit Embedded STT-MRAM, manufactured in TSMC's 45 nm LP technology at the Symposium on VLSI Circuits.[9]

In May 2011, Russian Nanotechnology Corp. announced an investment of $300 million in Crocus Nano Electronics (a joint venture with Crocus Technology) which will build an MRAM factory in Moscow, Russia.

In 2012 Everspin Technologies released the first commercially available DDR3 dual in-line memory module ST-MRAM which has a capacity of 64 Mb.[10]

In June 2019 Everspin Technologies started pilot production for 28 nm 1 Gb STT-MRAM chips.[11]

In December 2019 Intel demonstrated STT-MRAM for L4-cache [12]

In 2022 TechInsights finds 16Mb embedded STT-MRAM memory in the FitBit Luxe fitness tracker's MCU and that of several other commercially available wearable products. [13]

Other companies working on STT-RAM include Avalanche Technology, Crocus Technology[14] and Spin Transfer Technologies.[15]

See also

External links

Notes and References

  1. 10.1016/j.mattod.2017.07.007. Spintronics based random access memory: A review. Materials Today. 20. 9. 530. 2017. Bhatti. Sabpreet. Sbiaa. Rachid. Hirohata. Atsufumi. Ohno. Hideo. Fukami. Shunsuke. Piramanayagam. S.N. free. 10356/146755. free.
  2. 10.1016/j.jmmm.2007.12.019. 0304-8853. 320. 7. 1190–1216. Ralph. D. C.. M. D.. Stiles. Spin transfer torques. Journal of Magnetism and Magnetic Materials. April 2008. 0711.4608. 2008JMMM..320.1190R. 3209246.
  3. Web site: Maiken . Eric . Nonvolatile random access memory device . patents.google.com . Japan Patent Office . 20 May 2023.
  4. Book: Hosomi . M . IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest . A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram . IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest . December 2005 . 459–462 . 10.1109/IEDM.2005.1609379 . 0-7803-9268-X . 17635524 . https://ieeexplore.ieee.org/document/1609379/authors . 20 May 2023.
  5. Web site: Grandis press release describing partnership with Hynix. 2008-08-15. Grandis. 1 April 2008. 14 April 2012. https://web.archive.org/web/20120414121112/http://grandisinc.com/pdf/Grandis_PR_Apr01_2008.pdf.
  6. Web site: Hynix press release describing partnership with Grandis. 15 August 2008. Hynix. 2 April 2008.
  7. Web site: Session 8-4: 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell. https://web.archive.org/web/20120312040148/http://www.vlsisymposium.org/2009/circuits/cir_abstract/8-4.htm. 12 March 2012. vlsisymposium.org.
  8. http://www.foxbusiness.com/technology/2011/08/01/samsung-buys-grandis-as-mram-moves-toward-mainstream/#ixzz1TpEGFRmD
  9. A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance. 2011 Symposium on VLSI circuits (VLSIC). IEEE. 15–17 June 2011. 2158-5601. 978-1-61284-175-5. Kim. J.P.. Qualcomm Inc., San Diego, CA, USA. Taehyun Kim. Wuyang Hao. Rao. H.M.. Kangho Lee. Xiaochun Zhu. Xia Li. Wah Hsu. Kang. S.H.. Matt. N.. Yu. N.. 30 November 2019. 1 July 2017. https://web.archive.org/web/20170701173537/http://ieeexplore.ieee.org/document/5986428. live.
  10. Web site: Everspin ships first ST-MRAM memory with 500X performance of flash. Computerworld. 25 September 2014. 12 November 2012.
  11. Web site: Everspin enters pilot production phase for the world's First 28 nm 1 Gb STT-MRAM component Everspin. www.everspin.com. 25 June 2019.
  12. Web site: Intel demonstrates STT-MRAM for L4 cache. 10 December 2019 .
  13. Web site: TSMC 22ULL eMRAM Die removed from Ambiq™ Apollo4 cache. 20 June 2023 .
  14. Web site: Crocus press release describing MRAM new prototype. crocus-technology.com. Crocus. 1 October 2009. https://web.archive.org/web/20120420153006/http://www.crocus-technology.com/pr-10-01-09.html. 20 April 2012.
  15. Web site: Interview with Vincent Chun from Spin transfer technologies. Mram-info.com. 7 February 2014.

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