| Shakti | |
| Designfirm: | Indian Institute of Technology, Madras |
| Manuf1: | Intel |
| Manuf2: | Semi-Conductor Laboratory |
| Application: | SoC, development boards, based software platform, IOT |
| Arch: | RISC-V |
| Model1: | E-Class |
| Model2: | C-Class |
| Model3: | I-Class |
| Model4: | M-Class |
| Model5: | S-Class |
| Model6: | H-Class |
SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at Indian Institute of Technology, Madras to develop the first indigenous Indian industrial-grade processor.[1] The aim of SHAKTI initiative includes building an opensource production-grade processor, complete system on chips (SoCs), development boards and SHAKTI based software platform. The primary focus of the team is architecture research to develop SoCs, which is competitive with commercial offerings in the market concerning area, power and performance. All the source codes for SHAKTI are open-sourced under the Modified BSD License. The project was funded by the Ministry of Electronics and Information Technology (MeITY), Government of India.[2]
SHAKTI processors are based on the RISC-V ISA. The processors are designed to have either 22 nm FinFET or 180 nm CMOS technology nodes depending on the manufacturing foundry.
SHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".
The E and C-classes core are aimed at Internet of things (IoT), embedded and desktop markets. The processor design is free of any royalty and is open-sourced under the modified BSD License.[3]
E-class and C-class core are both implemented in Bluespec SystemVerilog (BSV) language.
The SHAKTI project aims to build 6 variants of processors based on the RISC-V ISA.
The E-class are 32/64 bit microcontrollers capable of supporting all extensions of the RISC-V ISA, aimed at low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM’s M-class (Cortex-M series) cores. It is capable of running real-time operating systems like FreeRTOS, Zephyr and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls and robotic platforms.[4] [5]
E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).[6]
The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It targets mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.
C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection.[7]
The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.[8] [9]
A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance targets.
The S-Class is a 64-bit superscalar, multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2–3 GHz.
The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.
These are experimental/research projects which focus on developing a high security and fault tolerant processor.
The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.[10]
The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.[11]
Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far.
RIMO is the code name of the SHAKTI C-class based SoC that has been taped-out at Semi-Conductor Laboratory (SCL) at Mohali using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP).
CREEK is the code name of the SHAKTI C-class based SoC that has been taped-out at Intel's Oregon fab using a 22nm FinFET process. The 16mm² chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA).
Moushik is the code name of the SHAKTI E-class based SoC that has been taped-out at SCL using 180 nm process technology. It operates in frequency of 100 MHz and developed along with a motherboard called Ardonyx 1.0.[12]
Some of the features of RIMO and Risecreek are as follows:
There are development boards for both E and C class of processors. The details on the board support for different classes of processors are given below.
Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers.[13]