The SDS Sigma series is a series of third generation computers[1] [2] [3] that were introduced by Scientific Data Systems of the United States in 1966.[4] The first machines in the series are the 16-bit Sigma 2 and the 32-bit Sigma 7; the Sigma 7 was the first 32-bit computer released by SDS. At the time, the only competition for the Sigma 7 was the IBM 360.
Memory size increments for all SDS/XDS/Xerox computers are stated in kwords, not kbytes. For example, the Sigma 5 base memory is 16K 32-bit words (64K bytes). Maximum memory is limited by the length of the instruction address field of 17 bits, or 128K words (512K bytes). Although this is a trivial amount of memory in today's technology, Sigma systems performed their tasks exceptionally well, and few were deployed with, or needed, the maximum 128K word memory size.
The CII 10070 computer was a rebadged Sigma 7 and served as a basis for the upgraded, yet still compatible, Iris 50 and Iris 80 computers. The Xerox 500 series computers, introduced starting in 1973, were also compatible upgrades to the Sigma systems using newer technology.
In 1975, Xerox sold its computer business to Honeywell, Inc. which continued support for the Sigma line for a time.
The Sigma 9 may hold the record for the longest lifetime of a machine selling near the original retail price. Sigma 9 computers were still in service in 1993. In 2011, the Living Computer Museum in Seattle, Washington acquired a Sigma 9 from a service bureau (Applied Esoterics/George Plue Estate) and has made it operational.[5] That Sigma 9 CPU was at the University of Southern Mississippi until Nov. 1985 when Andrews University purchased it and took it to Michigan. In February 1990, Andrews University via Keith Calkins sold and delivered it to Applied Esoterics in Flagstaff, Arizona. Keith Calkins made the Sigma 9 functional for the museum in 2012/13 and brought up the CP-V operating system in Dec. 2014. The various other system components came from other user sites, such as Marquette, Samford and Xerox/Dallas.
Source: [6]
| Model | Date | Floating point | Decimal | Byte string | Memory map | Max memory (kwords) | |
|---|---|---|---|---|---|---|---|
| Sigma 7 | 1966 | optional | optional | standard | optional | 128 | |
| Sigma 5 | 1967 | optional | N/A | N/A | N/A | 128 | |
| Sigma 6 | 1970 | optional | standard | standard | standard | 128 | |
| Sigma 9 | 1971 | standard | standard | standard | standard | 512 | |
| Sigma 8 | 1972 | standard | N/A | N/A | N/A | 128 | |
| Sigma 9 model 2 | ? | standard | standard | standard | standard | 256 | |
| Sigma 9 model 3 | 1973 | standard | N/A | N/A | standard | 512 |
| Model | Date | Max memory (kwords) | |
|---|---|---|---|
| Sigma 2 | 1966 | 64 | |
| Sigma 3 | 1969 | 64 |
The format for memory-reference instructions for the 32-bit Sigma systems is as follows:
+-+--------------+--------+------+---------------------------+
|*| Op Code | R | X | Reference address |
+-+--------------+--------+------+---------------------------+
bit 0 1 7 8 1 1 1 1 3
1 2 4 5 1
Bit 0 indicates indirect address.
Bits 1-7 contain the operation code (opcode)
Bits 8-11 encode a register operand (0:15)
Bits 12-14 encode an index register (1:7). 0 indicates no indexing.
Bits 16-31 encode the address of a memory word.
For the Sigma 9, when real extended addressing is enabled, the reference address field is interpreted differently depending on whether the high-order bit is 0 or 1:
+-+--------------+--------+------+-+-------------------------+
| | | | |0| Address in 1st 64K words|
|*| Op Code | R | X +-+-------------------------+
| | | | |1| Low 16 bits of address |
+-+--------------+--------+------+-+-------------------------+
bit 0 1 7 8 1 1 1 1 1 3
1 2 4 5 6 1
If the high-order bit is 0, the lower 16 bits of the address refer to a location in the first 64K words of main memory; if the high-order bit is 1, the lower 16 bits of the address refer to a location in a 64K-word block of memory specified by the Extension Address in bits 42-47 of the Program Status Doubleword, with the Extension Address being concatenated with the lower 16 bits of the reference address to form the physical address.
Sigma systems provided a range of performance, roughly doubling from Sigma 5, the slowest, to Sigma 9 Model 3, the fastest. For example, 32-bit fixed point multiply times ranged from 7.2 to 3.8 μs; 64-bit floating point divide ranged from 30.5 to 17.4 μs.
Most Sigma systems included two or more blocks of 16 general-purpose registers. Switching blocks is accomplished by a single instruction (LPSD), providing fast context switching, since registers do not have to be saved and restored.
Memory in the Sigma systems can be addressed as individual bytes, halfwords, words, or doublewords.
All 32-bit Sigma systems except the Sigma 5 and Sigma 8 used a memory map to implement virtual memory. The following description applies to the Sigma 9, other models have minor differences.
The effective virtual address of a word is 17 bits wide. Virtual addresses 0 thru 15 are reserved to reference the corresponding general purpose register, and are not mapped. Otherwise, in virtual memory mode the high-order eight bits of an address, called virtual page number, are used as an index to an array of 256 13-bit memory map registers. The thirteen bits from the map register plus the remaining nine bits of the virtual address form the address used to access real memory.
Access protection is implemented using a separate array of 256 two-bit access control codes, one per virtual page (512 words), indicating a combination of read/write/execute or no access to that page.
Independently, an array of 256 2-bit access control registers for the first 128k words of real memory function as a "lock-and-key" system in conjunction with two bits in the program status doubleword. The system allows pages to be marked "unlocked", or the key to be a "master key". Otherwise the key in the PSD had to match the lock in the access register in order to reference the memory page.
Input/output is accomplished using a control unit called an IOP (Input-output processor). An IOP provides an 8-bit data path to and from memory. Systems support up to 8 IOPs, each of which can attach up to 32 device controllers.[7] [8]
An IOP can be either a selector I/O processor (SIOP) or a multiplexer I/O processor (MIOP). The SIOP provides a data rate up to 1.5 megabytes per second (MBPS), but allows only one device to be active at a time. The MIOP, intended to support slow speed peripherals allows up to 32 devices to be active at any time, but provides only a .3 MBPS aggregate data rate.
The primary mass storage device, known as a RAD (random-access disk), contains 512 fixed heads and a large (approx 600 mm/24 in diameter) vertically mounted disk spinning at relatively low speeds. Because of the fixed head arrangement, access is quite fast. Capacities range from 1.6 to 6.0 megabytes and are used for temporary storage. Large-capacity multi-platter disks are employed for permanent storage.
| Device | Device type | Capacity [MB] | Avg seek time [ms] | Avg rotational delay [ms] | Avg transfer rate [kB/s] | |
|---|---|---|---|---|---|---|
| 3214 | RAD | 2.75 | N/A | 8.5 | 647 | |
| 7202 | RAD | .7 | N/A | 17 | 166 | |
| 7203 | RAD | 1.4 | N/A | 17 | 166 | |
| 7204 | RAD | 2.8 | N/A | 17 | 166 | |
| 7232 | RAD | 6.0 | N/A | 17 | 355 | |
| 3231 | Cartridge disk | 2.4 removable | 38 | 12.5 | 246 | |
| 3232 | Cartridge disk | 4.9 removable | 38 | 12.5 | 246 | |
| 3233 | Cartridge disk | 4.9 fixed 4.9 removable | 38 | 12.5 | 246 | |
| 3242 | Cartridge disk | 5.7 removable | 38 | 12.5 | 286 | |
| 3243 | Cartridge disk | 5.7 fixed 5.7 removable | 38 | 12.5 | 286 | |
| 7251 | Cartridge disk | 2.3 removable | 38 | 12.5 | 225 | |
| 7252 | Cartridge disk | 2.3 fixed 2.3 removable | 38 | 12.5 | 225 | |
| 3277 | Removable disk | 95 | 30 | 8.3 | 787 | |
| 7271 | Removable disk | 46.8 | 35 | 12.5 | 245 |
The Sigma 7611 Character Oriented Communications subsystem (COC) supports one to seven Line Interface Units (LIUs). Each LIU can have one to eight line interfaces capable of operating in simplex, half-duplex, or full-duplex mode. The COC was "intended for low to medium speed character oriented data transmissions."[9]
The optional Communication Input/Output Processor or CIOP handled upt to 128 communication lines at speeds from 128 to 9600 baud. It used 1K of dedicated mainframe memory for control and line status.[10]
The System Control Unit (SCU) was a "microprogrammable data processor" which can interface to a Sigma CPU, and "to peripheral and analog devices, and to many kinds of line protocol."[11] The SCU executes horizontal microinstructions with a 32-bit word length. A cross-assembler running on a Sigma system can be used to create microprograms for the SCU.
The Sigma 5 computer owned by Carnegie Mellon University was donated to the Computer History Museum in 2002. The system consists of five full-size cabinets with a monitor, control panel and a printer. It is possibly the last surviving Sigma 5 that is still operational.[12]
The Sigma 5 sold for US$300,000 with 16 kilowords of random-access magnetic-core memory, with an optional memory upgrade to 32 kW for an additional $50,000. The hard disk drive had a capacity of 3 megabytes.[13]
Sigma 5 and 8 systems lack the memory map feature,The Sigma 5 is supported by the Basic Control Monitor (BCM) and the Batch Processing Monitor (BPM). The Sigma 8 can run the Real-time Batch Monitor (RBM) as well as BPM/BTM.
The remaining models initially ran the Batch Processing Monitor (BPM), later augmented with a timesharing option (BTM); the combined system was usually referred to as BPM/BTM. The Universal Time-Sharing System (UTS) became available in 1971, supporting much enhanced time-sharing facilities. A compatible upgrade (or renaming) of UTS, Control Program V (CP-V) became available starting in 1973 and added real-time, remote batch, and transaction processing. A dedicated real-time OS, Control Program for Real-Time (CP-R) was also available for Sigma 9 systems. The Xerox Operating System (XOS), intended as an IBM DOS/360 replacement (not to be confused with PC DOS of a latter era), also runs on Sigma 6/7/9 systems, but never gained real popularity.
Some third party operating systems were available for Sigma Machines. One was named GEM (for Generalized Environmental Monitor), and was said to be "rather UNIX-like".[14] A second was named JANUS, from Michigan State University.[15] [16]
The Xerox software, called processors, available for CP-V in 1978 included:[17]
†Program product, chargeable
The Basic Control Monitor (BCM) for the Sigma 2 and 3 provided "Full real-time capability with some provision for batch processing in the background."[18] The Sigma 3 could also run RBM.
After Honeywell discontinued production of Sigma hardware — Xerox had sold most of the rights to Honeywell in July, 1975 — several companies produced or announced clone systems. The Telefile T-85, introduced in 1979, was an upward compatible drop-in replacement for 32-bit Sigmas. Ilene Industries Data Systems announced the MOD 9000, a Sigma 9 clone with an incompatible I/O architecture. Realtime Computer Equipment, Inc. designed the RCE-9, an upward compatible drop-in replacement that could also use IBM peripherals. The Modutest Mod 9 was redesigned and built by Gene Zeitler (President), Lothar Mueller (Senior VP) and Ed Drapell, is 100% hardware and software compatibility with the Sigma 9. It was manufactured and sold to Telefile, Utah Power and Light, Minnesota Power, Taiwan Power and Ohio College Library Center (OCLC).[19] [20] The French company CII produced Sigma 7 clones, the CII 10070, Iris 50, and the Iris 80.
As of 2023 the SIMH emulator can emulate a Sigma 5, 6, or 7 system.[21] A copy of CP-V version F00 is available to run on the simulator.[22]