Retiming is the technique of moving the structural location of latches or registers in a digital circuit to improve its performance, area, and/or power characteristics in such a way that preserves its functional behavior at its outputs. Retiming was first described by Charles E. Leiserson and James B. Saxe in 1983.[1]
The technique uses a directed graph where the vertices represent asynchronous combinational blocks and the directed edges represent a series of registers or latches (the number of registers or latches can be zero). Each vertex has a value corresponding to the delay through the combinational circuit it represents. After doing this, one can attempt to optimize the circuit by pushing registers from output to input and vice versa - much like bubble pushing. Two operations can be used - deleting a register from each input of a vertex while adding a register to all outputs, and conversely adding a register to each input of vertex and deleting a register from all outputs. In all cases, if the rules are followed, the circuit will have the same functional behavior as it did before retiming.
G:=(V,E)
e:=(u,v)
w(e)
e
d(v)
v
r(v)
wr(e):=w(e)+r(v)-r(u)
The most common use of retiming is to minimize the clock period. A simple technique to optimize the clock period is to search for the minimum feasible period (e.g. using binary search).
The feasibility of a clock period
T
T
W(u,v)
u
v
D(u,v)
u
v
W
D
| Given | w(e),W(u,v),D(u,v) T | ||
| Find | r(v):V\toZ | ||
| Such that | |||
r(u)-r(v) | \lew(e) | ||
r(u)-r(v) | \leW(u,v)-1 D(u,v)>T | ||
Alternatively, feasibility of a clock period
T
r(v)
| Given | w(e),d(v) T | ||
| Find | r(v):V\toZ R(v):V\tol{R} | ||
| Such that | |||
r(v)-R(V) | \le-d(v)/T | ||
R(v)-r(v) | \le1 | ||
r(u)-r(v) | \lew(e) | ||
R(u)-R(v) | \lew(e)-d(v)/T | ||
Alternate formulations allow the minimization of the register count and the minimization of the register count under a delay constraint. The initial paper includes extensions that allow the consideration of fan-out sharing and a more general delay model. Subsequent work has addressed the inclusion of register delays,[3] load-dependent delay models,[3] and hold constraints.[4]
Retiming has found industrial use, albeit sporadic. Its primary drawback is that the state encoding of the circuit is destroyed, making debugging, testing, and verification substantially more difficult. Some retimings may also require complicated initialization logic to have the circuit start in an identical initial state. Finally, the changes in the circuit's topology have consequences in other logical and physical synthesis steps that make design closure difficult.
Clock skew scheduling is a related technique for optimizing sequential circuits. Whereas retiming relocates the structural position of the registers, clock skew scheduling moves their temporal position by scheduling the arrival time of the clock signals. The lower bound of the achievable minimum clock period of both techniques is the maximum mean cycle time (i.e. the total combinational delay along any path divided by the number of registers along it).