Quality intellectual property metric explained

The quality intellectual property metric (QIP) is an international standard, developed by Virtual Socket Interface Alliance (VSIA) ^[1] for measuring Intellectual Property (IP) or Silicon intellectual property (SIP) quality and examining the practices used to design, integrate and support the SIP. SIP hardening is required to facilitate the reuse of IP in integrated circuit design.

Background and importance

Many computer processors use a system-on-a-chip (SoC) design, which is intended to include all of a device's functions on a single chip. As a result, these chips need to include numerous technical standards that the device will use. One solution to designing such a chip is the reuse of high quality IP. Reusing IP from others means that the chip designer does not need to redesign these elements. IP quality is the key to successful SoC designs, but it is one of the SoC’s most challenging problems.

QIP metric allows both the IP designers and IP integrators to measure the quality of an IP core against a checklist of critical issues.
IP integrators make use of the IP cores into their own design and deliver final integrated circuit for an application, e.g. an integrated circuit designer of iPhone main processor IC (ARM architecture CPU) integrates other IP cores like USB 2.0, DSP, MP4 decoder, etc.,^[2] so that the additional features of USB 2.0, MP4 decoder, etc. can be easily embedded into the final IC.
The QIP typically consists of interactive Microsoft Excel spreadsheets with sets of questions to be answered by the IP vendor.

SIP quality measure framework

Hong Kong Science and Technology Parks Corporation (HKSTP) and Hong Kong University of Science and Technology (HKUST) started to develop a SIP verification and quality measures framework in 2005, based on QIP metric. The objective is to develop a technical framework for SIP quality measures and evaluation based on QIP. Third-party SIP evaluation service is provided by HKSTP, so that IP integrators can know the quality of their desired SIP cores.^[3]

Integrated circuit (IC) designers have developed their own IC design, and such design can be reused by other IC designers. Other IC designers can reduce their risk of IC design, because such parts of design (IP cores) are well established and known to work well. But other IC designers do not know the quality of such IP cores provided. The original IP providers cannot provide the IP cores to other IC designers for evaluation, as it could allow competitors to steal their technologies. The solution is to have a third-party review the quality and value of the IP.

HKSTP is the third party between them and can act as a judge body, to evaluate the quality of IP cores of various IP providers, based on the public standard QIP metric. Other IP designers can know and choose their IP provider, based on the information provided by the third party, HKSTP. The IP providers can also get the evaluation report and improve the quality of their IP cores.

Soft and hard SIP

There are soft SIP and hard SIP verification and quality measures.

Soft IP comes with design source code in the form of synthesizable HDL (Hardware description language) code (VHDL and Verilog are HDL).
Hard IP is a design macro and model without HDL code available; they are optimized for power, size or performance, and mapped to a specific Process technology. Also refer to SIP hardening.

Notes and References

http://www.vsia.org VSIA documents
Book: Reuse Methodology Manual for System-on-a-Chip Designs. 978-0387740980. Michael. Keating. Pierre. Bricaud. 11 September 2007 . Springer.
Web site: Greater China Semiconductor Intellectual Property Trading Center . August 15, 2008 . dead . https://web.archive.org/web/20070908095553/http://www.gcsiptc.org/ . September 8, 2007 . GCSIPTC