Physical coding sublayer explained

The physical coding sublayer (PCS) is a networking protocol sublayer in the Fast Ethernet, Gigabit Ethernet, and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the physical medium attachment (PMA) sublayer and the media-independent interface (MII). It is responsible for data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, and lane block synchronization and deskew.[1]

Description

The Ethernet PCS sublayer is at the top of the Ethernet physical layer (PHY). The hierarchy is as follows:

x58+x39+1

scrambling/descrambling

x7+x6+1

scrambling/descrambling

Specifications

10 Mbit/s Ethernet

Fast Ethernet

Gigabit Ethernet

2.5 and 5 Gigabit Ethernet

10 Gigabit Ethernet

25 Gigabit Ethernet

40/100 Gigabit Ethernet

See also

References

External links

Notes and References

  1. Book: Spurgeon, Charles . Ethernet: The Definitive Guide . O'Reilly . 2014 . 198 . 978-1449361846 .
  2. IEEE 802.3 1.4 Definitions
  3. IEEE 802.3 Clause 24.1.4.1
  4. IEEE 802.3-2012 Clause 36
  5. IEEE 802.3-2012 Clause 40
  6. IEEE 802.3 48. Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X
  7. IEEE 802.3 Clause 55.3.2
  8. Web site: IEEE 802.3by 25G Ethernet TF, A BASELINE PROPOSAL FOR RS, PCS, AND FEC . 2015-01-12 . 2016-08-06.
  9. IEEE 802.3 Clauses 82-89