Paul Richman Explained

Paul Richman
Birth Date:	17 November 1942
Birth Place:	New York
Nationality:	American
Fields:	Semiconductor physics
Workplaces:	General Telephone and Electronics Standard Microsystems Corp

Paul Richman (born November 17, 1942) is an American semiconductor physicist and author.^{[1] [2]}

Education

In 1963, Richman studied at M.I.T. and graduated with a Bachelor of Science in electrical engineering. In 1964, he earned a Master of Science in electrical engineering from Columbia University.^[3]

Career

In 1971, Richman co-founded Standard Microsystems Corp (SMSC) as a research and development firm.^{[4] [5]} Before co-founding SMSC, he worked as a semiconductor physicist at General Telephone and Electronics.^[6] In 1987, he moved to Japan with his family and started a collaboration called Standard Microsystems Japan.^[4] Between 1971 and 1999, he served as the chief executive officer, president and chairman of Standard Microsystems.^{[7] [8]} During his tenure, SMSC became the largest chip maker on Long Island, and Intel Corp acquired a stake in the company.^{[4] [9]} Newsday has called him a pioneer in the computer chip industry.^[4] He introduced a method for decreasing the size of chips by moving transistors closer together while increasing operating speeds and as a result devices operate quickly and efficiently.^[4]

As an academic, Richman served as a visiting professor of electrical engineering at the City University of New York between 1974 and 1975 and at the State University of New York at Stony Brook between 1975 and 1987.^[10]

From 1998 to 2002, he served on the Massachusetts Institute of Technology's Visiting Committee for Electrical Engineering and Computer Science.

Richman developed and held the basic patent for COPLAMOS technology, which pioneered the use of field-doped, locally-oxidized structures in metal–oxide–semiconductor (M.O.S.) integrated circuits.^[11]

Awards

• 1978: Annual Achievement Award from Electronics (magazine) for his contributions to the development of microchips.^[12]
• 1982: Elected a Fellow of the Institute of Electrical and Electronics Engineers, the IEEE.^[13]
• 1998: IEEE's Harold A. Wheeler Award.
• 2000: IEEE's Third Millennium medal.^[14]
• 2012: Elected to the Long Island Technology Hall of Fame.^[15]

Patents

• Complementary Enhancement Type MOS Transistors. ^[16]
• Method for Manufacturing Metal-Oxide Silicon Devices. ^[17]
• Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer. ^[18]
• Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation.^[19]
• Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer.^[20]
• Hermetic plastic dual-in-line package for a semiconductor integrated circuit.^[21]
• Solid State Field Effect Device.^[22]
• Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate.^[23]
• MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions.^[24]
• Bipolar MOS Field Effect Transistor.^[25]
• MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions.^[26]
• Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask.^[27]
• Integrated MOS circuit.^[28]
• Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained.^[29]
• MOS Integrated Circuit Structure and Method for Its Fabrication.^[30]

Notes and References

1. Web site: SMSC sold to Arizona company for $939M. Newsday.
2. News: BUSINESS PEOPLE. The New York Times . July 4, 1979. NYTimes.com.
3. Web site: Alumni of Columbia Engineering — Greater New York City Area . alumnius.net.
4. Web site: THE SCOOP. Newsday. March 30, 2011. James. Bernstein. .
5. Web site: Leading chip firm stumbles. Crain's. September 19, 2006 .
6. Web site: Selling Technology's Daydreams. The New York Times. .
7. Web site: SMSC founder retires as CEO.
8. Web site: Standard Microsystems. WSJ. .
9. Web site: Intel buys stake in Hauppauge chip maker. .
10. Web site: Richman Steps Down From SMSC.
11. News from region 1 . IEEE Spectrum . 1980 . 17 . 1 . 110 . 10.1109/MSPEC.1980.6330239 . 1939-9340.
12. Web site: 1978 Award for Achievement . McGraw Hill.
13. Web site: IEEE Long Island Section: 2015 Annual Awards Banquet . ieee.li.
14. Web site: IEEE 2006 Annual Award Ceremony . IEEE Long Island . October 27, 2022.
15. Web site: The 2012 LITHF Inductees . stonybrook.
16. Web site: Complementary Enhancement Type MOS Transistors. . USPTO.
17. Web site: Method for Manufacturing Metal-Oxide Silicon Devices . USPTO.
18. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/3867196 Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer
19. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4080718 Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation.
20. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4600933 Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer.
21. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4298769 Hermetic plastic dual-in-line package for a semiconductor integrated circuit.
22. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/3544864 Solid State Field Effect Device.
23. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/3493824 Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate.
24. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4023195 MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions.
25. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/3500138 Bipolar MOS Field Effect Transistor.
26. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/3751722 MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions.
27. https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4282647 Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask.
28. https://patents.google.com/patent/DE2214935C2/en?inventor=Paul+Richman&page=1 Integrated MOS circuit.
29. https://patents.google.com/patent/FR2484140A1/en?inventor=Paul+Richman&page=1 Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained.
30. https://patents.google.com/patent/GB2123605A/en?inventor=Paul+Richman&page=2 MOS Integrated Circuit Structure and Method for Its Fabrication.