PL-4 or POS-PHY Level 4 was the name of the interface that the interface SPI-4.2 is based on. It was proposed by PMC-Sierra to the Optical Internetworking Forum. The name means Packet Over SONET Physical layer level 4. PL-4 was developed by PMC-Sierra in conjunction with the Saturn Development Group.
There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used between devices in the Packet over SONET and Optical Transport Network, which are the principal protocols used to carry the internet between cities.
PL-4 was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems. A typical application of PL-4 (SPI-4.2) is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace.
The interface consists of (per direction):
The clocking is Source-synchronous and operates around 700 MHz. Implementations of SPI-4.2 (PL-4) have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets.
The name is an acronym of an acronym of an acronym as the P in PL stands for POS-PHY and the S in POS-PHY stands for SONET (Synchronous Optical Network).
PL-4 is a descendant of PL-3 which itself is a descendant of the ATM Forum UTOPIA family of standards. The UTOPIA standards were developed by the SATURN Development Group for use in ATM systems.