Tegra Explained

Tegra is a system on a chip (SoC) series developed by Nvidia for mobile devices such as smartphones, personal digital assistants, and mobile Internet devices. The Tegra integrates an ARM architecture central processing unit (CPU), graphics processing unit (GPU), northbridge, southbridge, and memory controller onto one package. Early Tegra SoCs are designed as efficient multimedia processors. The Tegra-line evolved to emphasize performance for gaming and machine learning applications without sacrificing power efficiency, before taking a drastic shift in direction towards platforms that provide vehicular automation with the applied "Nvidia Drive" brand name on reference boards and its semiconductors; and with the "Nvidia Jetson" brand name for boards adequate for AI applications within e.g. robots or drones, and for various smart high level automation purposes.

History

The Tegra APX 2500 was announced on February 12, 2008. The Tegra 6xx product line was revealed on June 2, 2008,^[1] and the APX 2600 was announced in February 2009. The APX chips were designed for smartphones, while the Tegra 600 and 650 chips were intended for smartbooks and mobile Internet devices (MID).^[2]

The first product to use the Tegra was Microsoft's Zune HD media player in September 2009, followed by the Samsung M1.^[3] Microsoft's Kin was the first cellular phone to use the Tegra;^[4] however, the phone did not have an app store, so the Tegra's power did not provide much advantage. In September 2008, Nvidia and Opera Software announced that they would produce a version of the Opera 9.5 browser optimized for the Tegra on Windows Mobile and Windows CE.^{[5] [6]} At Mobile World Congress 2009, Nvidia introduced its port of Google's Android to the Tegra.

On January 7, 2010, Nvidia officially announced and demonstrated its next generation Tegra system-on-a-chip, the Nvidia Tegra 250, at Consumer Electronics Show 2010.^[7] Nvidia primarily supports Android on Tegra 2, but booting other ARM-supporting operating systems is possible on devices where the bootloader is accessible. Tegra 2 support for the Ubuntu Linux distribution was also announced on the Nvidia developer forum.^[8]

Nvidia announced the first quad-core SoC at the February 2011 Mobile World Congress event in Barcelona. Though the chip was codenamed Kal-El, it is now branded as Tegra 3. Early benchmark results show impressive gains over Tegra 2,^{[9] [10]} and the chip was used in many of the tablets released in the second half of 2011.

In January 2012, Nvidia announced that Audi had selected the Tegra 3 processor for its In-Vehicle Infotainment systems and digital instruments display.^[11] The processor will be integrated into Audi's entire line of vehicles worldwide, beginning in 2013. The process is ISO 26262-certified.^[12]

In summer of 2012 Tesla Motors began shipping the Model S all electric, high performance sedan, which contains two NVIDIA Tegra 3D Visual Computing Modules (VCM). One VCM powers the 17-inch touchscreen infotainment system, and one drives the 12.3-inch all digital instrument cluster."^[13]

In March 2015, Nvidia announced the Tegra X1, the first SoC to have a graphics performance of 1 teraflop. At the announcement event, Nvidia showed off Epic Games' Unreal Engine 4 "Elemental" demo, running on a Tegra X1.

On October 20, 2016, Nvidia announced that the Nintendo Switch hybrid video game console will be powered by Tegra hardware.^[14] On March 15, 2017, TechInsights revealed the Nintendo Switch is powered by a custom Tegra X1 (model T210), with lower clockspeeds.^[15]

Models

Tegra APX

Tegra APX 2500

• Processor: ARM11 600 MHz MPCore (originally GeForce ULV)
  • Suffix: APX (formerly CSX)
• Memory: NOR or NAND flash, Mobile DDR
• Graphics: Image processor (FWVGA 854×480 pixels)
  • Up to 12 megapixels camera support
  • LCD controller supports resolutions up to 1280×1024
• Storage: IDE for SSD
• Video codecs: up to 720p MPEG-4 AVC/H.264 and VC-1 decoding
• Includes GeForce ULV support for OpenGL ES 2.0, Direct3D Mobile, and programmable shaders
• Output: HDMI, VGA, composite video, S-Video, stereo jack, USB
• USB On-The-Go

Tegra APX 2600

• Enhanced NAND flash
• Video codecs:^[16]
  • 720p H.264 Baseline Profile encode or decode
  • 720p VC-1/WMV9 Advanced Profile decode
  • D-1 MPEG-4 Simple Profile encode or decode

Tegra 6xx

Tegra 600

• Targeted for GPS segment and automotiveRed
• Processor: ARM11 700 MHz MPCore
• Memory: low-power DDR (DDR-333, 166 MHz)
• SXGA, HDMI, USB, stereo jack
• HD camera 720p

Tegra 650

• Targeted for GTX of handheld and notebook
• Processor: ARM11 800 MHz MPCore
• Low power DDR (DDR-400, 200 MHz)
• Less than 1 watt envelope
• HD image processing for advanced digital still camera and HD camcorder functions
• Display supports 1080p at 24 frame/s, HDMI v1.3, WSXGA+ LCD and CRT, and NTSC/PAL TV output
• Direct support for Wi-Fi, disk drives, keyboard, mouse, and other peripherals
• A complete board support package (BSP) to enable fast time to market for Windows Mobile-based designs

Tegra 2

The second generation Tegra SoC has a dual-core ARM Cortex-A9 CPU, an ultra low power (ULP) GeForce GPU,^[17] a 32-bit memory controller with either LPDDR2-600 or DDR2-667 memory, a 32 KB/32 KB L1 cache per core and a shared 1 MB L2 cache.^[18] Tegra 2's Cortex A9 implementation does not include ARM's SIMD extension, NEON. There is a version of the Tegra 2 SoC supporting 3D displays; this SoC uses a higher clocked CPU and GPU.

The Tegra 2 video decoder is largely unchanged from the original Tegra and has limited support for HD formats.^[19] The lack of support for high-profile H.264 is particularly troublesome when using online video streaming services.

Common features:

• CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
• 40 nm semiconductor technology

Model number	CPU			GPU			Memory				Adoption
	Processor	Cores	Frequency	Micro- architecture	Core configuration^1	Frequency	Type	Amount	Bus width	Band- width	Availability
AP20H (Ventana/Unknown)		2	1.0 GHz	VLIW-based VEC4 units^[20]	4:4:4:4^[21]	300 MHz	LPDDR2 300 MHz DDR2 333 MHz	?	32 bit single-channel	2.4 GB/s 2.7 GB/s	Q1 2010
T20 (Harmony/Ventana)						1 GHz-->						333 MHz	32-bit single-channel 300 MHz LPDDR2 (2.4 GB/sec) or 333 MHz DDR2 (2.7 GB/sec)-->	Q1 2010-->
AP25			1.2 GHz			400 MHz<					--	32-bit single-channel 300 MHz LPDDR2 (2.4 GB/sec) or 333 MHz DDR2 (2.7 GB/sec)-->	Q1 2011
T25											1.2 GHz-->	400 MHz-->		32-bit single-channel 300 MHz LPDDR2 (2.4 GB/sec) or 333 MHz DDR2 (2.7 GB/sec)-->	Q1 2011-->

¹ Pixel shaders : Vertex shaders : Texture mapping units : Render output units

Devices

Model	Devices
AP20H	Motorola Atrix 4G, Motorola Droid X2, Motorola Photon, LG Optimus 2X / LG Optimus Dual P990 / Optimus 2x SU660 (?), Samsung Galaxy R, Samsung Captivate Glide, T-Mobile G2X P999, Acer Iconia Tab A200 and A500, LG Optimus Pad, Motorola Xoom,^[22] Sony Tablet S, Dell Streak Pro,^[23] Toshiba Thrive^[24] tablet, T-Mobile G-Slate
AP25	Fusion Garage Grid 10
T20	Avionic Design Tamonten Processor Board,^[25] Notion Ink Adam tablet, Olivetti OliPad 100, ViewSonic G Tablet, ASUS Eee Pad Transformer, Samsung Galaxy Tab 10.1, Toshiba AC100, CompuLab Trim-Slice nettop, Velocity Micro Cruz Tablet L510, Acer Iconia Tab A100
	Tesla Motors Model S 2012~2017 and Model X 2015~2017 instrument cluster (IC)^[26] ^[27]

Tegra 3

NVIDIA's Tegra 3 (codenamed "Kal-El")^[28] is functionally a SoC with a quad-core ARM Cortex-A9 MPCore CPU, but includes a fifth "companion" core in what Nvidia refers to as a "variable SMP architecture".^[29] While all cores are Cortex-A9s, the companion core is manufactured with a low-power silicon process. This core operates transparently to applications and is used to reduce power consumption when processing load is minimal. The main quad-core portion of the CPU powers off in these situations.

Tegra 3 is the first Tegra release to support ARM's SIMD extension, NEON.

The GPU in Tegra 3 is an evolution of the Tegra 2 GPU, with 4 additional pixel shader units and higher clock frequency. It can also output video up to 2560×1600 resolution and supports 1080p MPEG-4 AVC/h.264 40 Mbit/s High-Profile, VC1-AP, and simpler forms of MPEG-4 such as DivX and Xvid.^[30]

The Tegra 3 was released on November 9, 2011.^[31]

Common features:

• CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
• 40 nm LPG semiconductor technology by TSMC

Model number	CPU			GPU			Memory				Adoption
	Processor	Cores	Frequency (multi- / single-core mode)	Micro- architecture	Core configuration^1	Frequency	Type	Amount	Bus width	Band- width	Availability
T30L		4+1	1.2 GHz / up to 1.3 GHz	VLIW-based VEC4 units	8:4:8:8^[32]	416 MHz		?	32 bit single-channel	5.3 GB/s^[33]	Q1 2012
T30			1.4 GHz / up to 1.5 GHz			520 MHz		?		4.3 GB/s 6.0 GB/s^[34]	Q4 2011
AP33												1.4 GHz / up to 1.5 GHz-->	520 MHz-->	32-bit single-channel 533 MHz LPDDR2-1066 (4.3 GB/sec) or 750 MHz DDR3-L (6.0 GB/sec)-->	Q4 2011-->
T33			1.6 GHz / up to 1.7 GHz				520 MHz-->			?	6.4 GB/s	Q2 2012

¹ Pixel shaders : Vertex shaders : Texture mapping units : Render output units

Devices

Model	Devices
AP33	LG Optimus 4X HD, HTC One X, XOLO Play T1000,^[35] Coolpad 8735
T30	Asus Eee Pad Transformer Prime (TF201),^[36] IdeaTab K2 / LePad K2,^[37] Acer Iconia Tab A510, Fuhu Inc. nabi 2 Tablet,^[38] Microsoft Surface RT,^[39] Lenovo IdeaPad Yoga 11,^[40] ^[41]
T30I	Tesla Model S 2012~2017 and Model X 2015~2017 media control unit (MCU)^[42]
T30L	Asus Transformer Pad TF300T, Microsoft Surface, Nexus 7 (2012),^[43] Sony Xperia Tablet S, Acer Iconia Tab A210, Toshiba AT300 (Excite 10),^[44] BLU Quattro 4.5,^[45] Coolpad 9070
T33	Asus Transformer Pad Infinity (TF700T), Fujitsu ARROWS X F-02E, Ouya, HTC One X+

Tegra 4

The Tegra 4 (codenamed "Wayne") was announced on January 6, 2013, and is a SoC with a quad-core CPU, but includes a fifth low-power Cortex A15 companion core which is invisible to the OS and performs background tasks to save power. This power-saving configuration is referred to as "variable SMP architecture" and operates like the similar configuration in Tegra 3.^[46]

The GeForce GPU in Tegra 4 is again an evolution of its predecessors. However, numerous feature additions and efficiency improvements were implemented. The number of processing resources was dramatically increased, and clock rate increased as well. In 3D tests, the Tegra 4 GPU is typically several times faster than that of Tegra 3.^[47] Additionally, the Tegra 4 video processor has full support for hardware decoding and encoding of WebM video (up to 1080p 60 Mbit/s @ 60fps).^[48]

Along with Tegra 4, Nvidia also introduced i500, an optional software modem based on Nvidia's acquisition of Icera, which can be reprogrammed to support new network standards. It supports category 3 (100 Mbit/s) LTE but will later be updated to Category 4 (150 Mbit/s).

Common features:

• CPU cache: L1: 32 KB instruction + 32 KB data, L2: 2 MB
• 28 nm HPL semiconductor technology

¹ Pixel shaders : Vertex shaders : Pixel pipelines (pairs 1x TMU and 1x ROP)

Tegra 4i

The Tegra 4i (codenamed "Grey") was announced on February 19, 2013. With hardware support for the same audio and video formats, but using Cortex-A9 cores instead of Cortex-A15, the Tegra 4i is a low-power variant of the Tegra 4 and is designed for phones and tablets. Unlike its Tegra 4 counterpart, the Tegra 4i also integrates the Icera i500 LTE/HSPA+ baseband processor onto the same die.

Common features:

• 28 nm HPM semiconductor technology
• CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB

¹ Pixel shaders : Vertex shaders : Pixel pipelines (pairs 1x TMU and 1x ROP)

Devices

Tegra K1

Nvidia's Tegra K1 (codenamed "Logan") features ARM Cortex-A15 cores in a 4+1 configuration similar to Tegra 4, or Nvidia's 64-bit Project Denver dual-core processor as well as a Kepler graphics processing unit with support for Direct3D 12, OpenGL ES 3.1, CUDA 6.5, OpenGL 4.4/OpenGL 4.5, and Vulkan.^{[73] [74]} Nvidia claims that it outperforms both the Xbox 360 and the PS3, whilst consuming significantly less power.^[75]

Support Adaptive Scalable Texture Compression.^[76]

In late April 2014, Nvidia shipped the "Jetson TK1" development board containing a Tegra K1 SoC and running Ubuntu Linux.^[77]

• Processor:
  • 32-bit variant quad-core ARM Cortex-A15 MPCore R3 + low power companion core
  • or 64-bit variant with dual-core Project Denver^[78] (variant once codenamed "Stark"^[79])
• GPU consisting of 192 ALUs using Kepler technology
• 28 nm HPM process
• Released in Q2 2014
• Power consumption: 8 watts^[75]

Model number	CPU			GPU				Memory				Adoption
	Processor	Cores	Frequency	Micro- architecture	Core configuration^1	Frequency	GFLOPS (FP32)	Type	Amount	Bus width	Band- width	Availability
T124^[80]	Cortex-A15 R3 (32-bit)	4+1	up to 2.3 GHz^[81]	GK20A (Kepler)	192:8:4^[82]	756–951 MHz	290–365^[83]	DDR3L LPDDR3	max 8 GB with 40-bit address extension^2	64 bit	17 GB/s	Q2 2014
T132	Denver (64-bit)	2	up to 2.5 GHz						max 8 GB	?	?	Q3 2014

¹ Unified Shaders : Texture mapping units : Render output units

² ARM Large Physical Page Extension (LPAE) supports 1 TiB (2⁴⁰ bytes). The 8 GiB limitation is part-specific.

Devices

Model	Devices
T124	Jetson TK1 development board,^[84] Nvidia Shield Tablet,^[85] Acer Chromebook 13,^[86] HP Chromebook 14 G3,^[87] Xiaomi MiPad,^[88] Snail Games OBox, UTStarcom MC8718, Google Project Tango tablet,^[89] Apalis TK1 System on Module,^[90] Fuze Tomahawk F1,^[91] JXD Singularity S192^[92]
T132	HTC Nexus 9^[93] ^[94]

In December 2015, the web page of wccftech.com published an article stating that Tesla is going to use a Tegra K1 based design derived from the template of the Nvidia Visual Computing Module (VCM) for driving the infotainment systems and providing visual driving aid in the respective vehicle models of that time.^[95] This news has, as of now, found no similar successor or other clear confirmation later on in any other place on such a combination of a multimedia with an auto pilot system for these vehicle models.

Tegra X1

Released in 2015, Nvidia's Tegra X1 (codenamed "Erista") features two CPU clusters, one with four ARM Cortex-A57 cores and the other with four ARM Cortex-A53 cores, as well as a Maxwell-based graphics processing unit.^{[96] [97]} It supports Adaptive Scalable Texture Compression.^[76] Only one cluster of cores can be active at once, with the cluster switch being handled by software on the BPMP-L. Devices utilizing the Tegra X1 have only been seen to utilize the cluster with the more powerful ARM Cortex-A57 cores. The other cluster with four ARM Cortex-A53 cores cannot be accessed without first powering down the Cortex-A57 cores (both clusters must be in the CC6 off state).^[98] Nvidia has removed the ARM Cortex-A53 cores from later versions of technical documentation, implying that they have been removed from the die.^{[99] [100]} The Tegra X1 was found to be vulnerable to a Fault Injection (FI) voltage glitching attack, which allowed for arbitrary code execution and homebrew software on the devices it was implemented in.^[101]

A revision (codenamed "Mariko") with greater power efficiency, known officially as Tegra X1+ was released in 2019,^[102] fixing the Fusée Gelée exploit. It's also known as T214 and T210B01.

• CPU

ARMv8 ARM Cortex-A57 quad-core (64-bit) + (unused?) ARM Cortex-A53 quad-core (64-bit)

• GPU

Maxwell-based 256 core GPU (Jetson Nano: only 128 cores)

• MPEG-4 HEVC VP8 encoding/decoding & VP9 decoding support^[103] (Jetson Nano: encoders are H.265, H.264/Stereo, VP8, JPEG; decoders are H.265, H.264/Stereo, VP8, VP9, VC-1, MPEG-2, JPEG)
• TSMC 20 nm process for the Tegra X1
• TSMC 16 nm process for the Tegra X1+.
• TDP

• • T210: 15 W,^[104] with average power consumption less than 10 W
  • Jetson Nano: 10 W (mode 0);^[105] mode 1: 5W (only 2 CPU cores @ 918 MHz, GPU @ 640 MHz)

Model number	SOC Variant	Process	CPU			GPU					Memory				Adoption
			Processor	Cores	Frequency^1	Micro- architecture	Core configuration^2	Frequency	GFLOPS (FP32)	GFLOPS (FP16)	Type	Amount^3	Bus width	Band- width^4	Availability
T210	ODNX02-A2TM670D-A1 TM670M-A2 TM671D-A2	TSMC 20 nm	Cortex-A57 + Cortex-A53^[106]	A57: 4 A53: 4	A57: 2.2 GHz^[107] A53: 1.3 GHz	GM20B (Maxwell)	256: 16:16	1000 MHz	512	1024	LPDDR3 / LPDDR4	8 GB	64 bit	25.6 GB/s	Q2 2015
	TM660M-A2				A57: 1.428 GHz A53: ? GHz		128:16:16	921 MHz	236	472	LPDDR3? / LPDDR4	4 GB			March 2019
T214 / T210b01	ODNX10-A1TM675M-A1	TSMC 16 nm	Cortex-A57	A57: 4	A57: 2.1 GHz^[108]	GM21B (Maxwell)^[109]	256:16:16	1267 MHz^[110]	649	1298	LPDDR4 /LPDDR4X	8 GB		34.1 GB/s	Q2 2019

¹ CPU frequency may be clocked differently than the maximum validated by Nvidia at the OEM's discretion

² Unified Shaders : Texture mapping units : Render output units

³ Maximum validated amount of memory, implementation is board specific

⁴ Maximum validated memory bandwidth, implementation is board specific

Devices

Model	SOC Variant	Devices
T210	ODNX02-A2	Nintendo Switch (2017, HAC-001) ^[111]
	TM670D-A1	Nvidia Shield Android TV (2015)
	TM670M-A2	Nvidia Shield Android TV (2017)
	TM660M-A2	Jetson Nano 4 GB, Jetson Nano 2 GB
	TM671D-A2	Google Pixel C
		Nvidia Jetson TX1 development board,^[112] Nvidia Drive CX & PX
T210b01	ODNX10-A1	Nintendo Switch (2019, HAC-001(-01)), Nintendo Switch: OLED Model (HEG-001), Nintendo Switch Lite (HDH-001)
	TM675M-A1	Nvidia Shield Android TV (2019)

Tegra X2

Nvidia's Tegra X2^{[113] [114]} (codenamed "Parker") features Nvidia's own custom general-purpose ARMv8-compatible core Denver 2 as well as code-named Pascal graphics processing core with GPGPU support.^[115] The chips are made using FinFET process technology using TSMC's 16 nm FinFET+ manufacturing process.^{[116] [117] [118]}

• CPU: Nvidia Denver2 ARMv8 (64-bit) dual-core + ARMv8 ARM Cortex-A57 quad-core (64-bit)
• RAM: up to 8 GB LPDDR4^[119]
• GPU: Pascal-based, 256 CUDA cores; type: GP10B^[120]

• TSMC 16 nm, FinFET process
• TDP: 7.5–15 W^[121]

¹ Unified Shaders : Texture mapping units : Render output units (SM count)

Devices

Model	Devices
T186	Nvidia Drive PX2 (variants), ZF ProAI 1.1^[124]
T186	Nvidia Jetson TX2
	Mercedes-Benz MBUX (infotainment system)^[125]
	1 unit along with 1 GPU semiconductor is part of the ECU for "Tesla vision" functionality in all Tesla vehicles since October 2016^[126] ^[127]
T186	Magic Leap One^[128] ^[129] (mixed environment glasses)
	Skydio 2 (drone)^[130]

Xavier

The Xavier Tegra SoC, named after the comic book character Professor X, was announced on 28 September 2016, and by March 2019, it had been released.^[131] It contains 7 billion transistors and 8 custom ARMv8 cores, a Volta GPU with 512 CUDA cores, an open sourced TPU (Tensor Processing Unit) called DLA (Deep Learning Accelerator).^{[132] [133]} It is able to encode and decode 8K Ultra HD (7680×4320). Users can configure operating modes at 10 W, 15 W, and 30 W TDP as needed and the die size is 350 mm².^{[134] [135] [136]} Nvidia confirmed the fabrication process to be 12 nm FinFET at CES 2018.^[137]

• CPU: Nvidia custom Carmel ARMv8.2-A (64-bit), 8 cores 10-wide superscalar^[138]
• GPU: Volta-based, 512 CUDA cores with 1.4 TFLOPS;^[139] type: GV11B^{[140] [120]}
• TSMC 12 nm, FinFET process
• 20 TOPS DL and 160 SPECint @ 20 W; 30 TOPS DL @ 30 W (TOPS DL = Deep Learning Tera-Ops)
  • 20 TOPS DL via the GPU based tensor cores
  • 10 TOPS DL (INT8) via the DLA unit that shall achieve 5 TFLOPS (FP16)^[139]
• 1.6 TOPS in the PVA unit (Programmable Vision Accelerator,^[141] for StereoDisparity/OpticalFlow/ImageProcessing)
• 1.5 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
• Video processor for 1.2 GPix/s encoding and 1.8 GPix/s decode^[139] including 8k video support^[135]
• MIPI-CSI-3 with 16 lanes^{[142] [143]}
• 1 Gbit/s Ethernet
• 10 Gbit/s Ethernet

Model number	SOC Variant	CPU			GPU					Memory				Adoption
		Processor	Cores	Frequency	Micro- architecture	Core configuration^1	Frequency	GFLOPS (FP32)	GFLOPS (FP16)	Type	Amount	Bus width	Band- width	Availability
T194^[144]		Carmel	8	up to 2.26 GHz	GV10B^[145] (Volta)	512:32:16 (8, 64)^[146]	854–1377 MHz	874–1410	1748–2820	LPDDR4X	16 GB	256-bit	137 GB/s	March 2019
NX (15W)	Carmel-->		TE860M-A2	2, 4 or 6	up to 1.4 GHz (Hexa and Quad Core) or up to 1.9 GHz (Dual Core)	GV10B (Volta)	384:24:16 (6, 48)^[147]	1100 MHz	845	1690	LPDDR4X	8 GB	128-bit	51.2 GB/s	March 2020
NX (10W)	Carmel-->			2 or 4	up to 1.2 GHz (Quad Core) or up to 1.5 GHz (Dual Core)			GV10B (Volta)-->	384:24:16 (6, 48)^[148] -->	800 MHz	614	1229	LPDDR4X	8 GB	128-bit	51.2 GB/s	March 2020

¹ Unified Shaders : Texture mapping units : Render output units (SM count, Tensor Cores)

Devices

Model	SOC Variant	Devices
T194		Nvidia Drive Xavier (Drive PX-series)^[149] (formerly named Xavier AI Car Supercomputer)
		Nvidia Drive Pegasus (Drive PX-series)
		Nvidia Drive AGX Xavier Developer Kit^[150]
		Nvidia Jetson AGX Xavier Developer Kit^[151]
		Nvidia Jetson Xavier
	TE860M-A2	Nvidia Jetson Xavier NX^[152]
		Nvidia Clara AGX^[153] "Clara AGX is based on NVIDIA Xavier and NVIDIA Turing GPUs."^[154]
		Bosch and Nvidia designed Self Driving System^[155]
		ZF ProAI^[156] ^[157]

On the Linux Kernel Mailing List, a Tegra194 based development board with type ID "P2972-0000" got reported: The board consists of the P2888 compute module and the P2822 baseboard.^[158]

Orin

Nvidia announced the next-gen SoC codename Orin on March 27, 2018, at GPU Technology Conference 2018.^[159] It contains 17 billion transistors and 12 ARM Hercules cores and is capable of 200 INT8 TOPs @ 65W.^[160]

The Drive AGX Orin board system family was announced on December 18, 2019, at GTC China 2019. Nvidia has sent papers to the press documenting that the known (from Xavier series) clock and voltage scaling on the semiconductors and by pairing multiple such chips a wider range of application can be realized with the thus resulting board concepts.^[161] In early 2021, Nvidia announced the Chinese vehicle company NIO will be using an Orin-based chip in their cars.^[162]

The so far published specifications for Orin are:

• CPU: 12× Arm Cortex-A78AE (Hercules) ARMv8.2-A (64-bit)^{[163] [164]}
• GPU: Ampere-based, 2048^[165] CUDA cores and 64 tensor cores¹; "with up to 131 Sparse TOPs of INT8 Tensor compute, and up to 5.32 FP32 TFLOPs of CUDA compute."^[166]
  • 5.3 CUDA TFLOPs (FP32)^[167]
  • 10.6 CUDA TFLOPs (FP16)^[167]
• Samsung 8 nm process^[167]
• 275 TOPS (INT8) DL^[167]
  • 170 TOPS DL (INT8) via the GPU
  • 105 TOPS DL (INT8) via the 2x NVDLA 2.0 units (DLA, Deep Learning Accelerator)
• 85 TOPS DL (FP16)^[167]
• 5 TOPS in the PVA v2.0 unit (Programmable Vision Accelerator for Feature Tracking)
• 1.85 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
• Video processor for ? GPix/s encoding and ? GPix/s decode
• 4× 10 Gbit/s Ethernet, 1× 1 Gbit/s Ethernet

¹ Orin uses the double-rate tensor cores in the A100, not the standard tensor cores in consumer Ampere GPUs.

Nvidia announced the latest member of the family, "Orin Nano" in September 2022 at the GPU Technology Conference 2022.^[168] The Orin product line now features SoC and SoM(System-On-Module) based on the core Orin design and scaled for different uses from 60W all the way down to 5W. While less is known about the exact SoC's that are being manufactured, Nvidia has publicly shared detailed technical specifications about the entire Jetson Orin SoM product line. These module specifications illustrate how Orin scales providing insight into future devices that contain an Orin derived SoC.

Notes and References

1. Web site: Techtree.com India > News > Hardware > Nvidia Rolls out "Tegra" Chips. https://web.archive.org/web/20080604024432/http://www.techtree.com/India/News/Nvidia_Rolls_out_Tegra_Processors/551-89833-581.html. dead. June 4, 2008. June 4, 2008.
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3. Web site: Nvidia prepara Tegra 3 a 1,5 GHz . TugaTech . 2011-01-27 . 2016-07-10 . October 16, 2017 . https://web.archive.org/web/20171016174636/https://tugatech.com.pt/t3108-nvidia-prepara-tegra-3-a-15-ghz . live .
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