The Motorola DSP56000 (also known as 56K) is a family of digital signal processor (DSP) chips produced by Motorola Semiconductor (later Freescale Semiconductor then NXP) starting in 1986[1] [2] [3] [4] [5] with later models are still being produced in the 2020s. The 56k series was intended mainly for embedded systems doing signal processing, but was also quite popular for a time in a number of computers, including the NeXT, Atari Falcon030 and SGI Indigo workstations all using the 56001.[6] Upgraded 56k versions are still used in audio equipment, radar systems, communications devices (like mobile phones) and various other embedded DSP applications. The 56000 was also used as the basis for the updated 96000, which was not commercially successful.
The DSP56000 uses fixed-point arithmetic, with 24-bit program words and 24-bit data words. It includes two 24-bit registers, which can also be referred to as a single 48-bit register. It also includes two 56-bit accumulators, each with an 8-bit "extension" (headroom); otherwise, the accumulators are similar to the other 24/48-bit registers. Being a Modified Harvard architecture processor, the 56k has three memory spaces+buses (and on-chip memory banks in some of the models): a program memory space/bus and two data memory space/bus. The stack area is allocated in a separate address space, which is called "Stack Memory Space",[7] distinct from the main memory address space.[8] The stack, which is used when subroutine calls and "long interrupt"s, is fifteen in depth.[8]
24 bits was selected as the basic word length because it gave the system a reasonable number range and precision for processing audio (sound), the 56000's main concern. 24 bits correspond to a dynamic range of 144 dB, sufficient in the 1980s when analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) rarely exceeded 20 bits. One example is ADSL applications, where filters typically require 20 bits of accuracy. The leftmost four bits are typically considered ample headroom to avoid overflow in calculations.
The processor is capable of carrying out 16.5 million instructions per second (MIPS) at the maximum specified clock speed of 33 MHz, and has hardware support for block-floating point FFT. It uses 5 V TTL levels and consumes approximately 0.4 W.
In most designs the 56000 is dedicated to one single task, because digital signal processing using special hardware is mostly real-time and does not allow any interruption. For less demanding tasks which are not time-critical, designers normally use a separate CPU or MCU.
The 56000 can execute a 1024-point complex Fast Fourier transform (FFT) in 59,898 clock cycles, taking 1.8 ms at 33 MHz,[9] or a rate of just over 555 operations per second, allowing both realtime decoding and encoding of reasonably advanced audio codecs such as MP3 for direct-to-disc recording purposes.[10] [11]
The addition of SIMD instructions to most desktop computer CPUs have meant that dedicated DSP chips like the 56000 have partly disappeared from some application fields, but they continue to be used widely in communications and other professional uses. To this end the 56800 series added a complete MCU which created a single-chip "DSPcontroller" solution, while the opposite occurred in the 68456, a 68000 with a 56000 on it.
A still quite prevalent model of the 56000 is the third generation 56300 family, starting with the 56301,[12] which features several models with special applications hard- and firmware built-in, like PCI interface logic, CRC processors, or audio companders. Core clock frequencies ranged up to 250 MHz.[13]
The 56000 provides a comprehensive suite of development tool, including a C Compiler, an Assembler, and an Instruction set simulator.[14] [15] [16]