The MaverickCrunch is a floating point math coprocessor core intended for digital audio. It was first presented by Cirrus Logic in June 2000[1] together with an ARM920T integer processor in their 200 MHz EP9302, EP9307, EP9312, and EP9315 System-on-Chip integrated circuits. it was seldom used in any of the devices based on those chips and the product line was discontinued on April 1, 2008.
The coprocessor has 16 64-bit registers which can be used for 32- or 64-bit integer and floating point operations and its floating point format is based on the IEEE-754 standard. It has its own instruction set which performs floating point addition, subtraction, multiplication, negation, absolute value, and comparisons as well as addition, multiplication and bit shifts on integers. It also has four 72-bit registers on which can perform a 32-bit multiply-and-accumulate instruction and a status register, as well as conversions between integer and floating point values and instructions to move data between itself and the ARM registers or memory.
It operates in parallel with the main processor, both processors receiving their instructions from a single 32-bit instruction stream. Thus, to use it efficiently, integer and floating point instructions must be interleaved so as to keep both processors busy.
Five versions of the EP93xx silicon were issued: "D0" and "D1"/"E0"/"E1" and "E2", with major revisions to the MaverickCrunch core between D0 and D1 to fix its worst bugs. All have a dozen or more hardware bugs which either give imprecise or garbage results or clobber registers or memory when certain sequences of instructions are executed in a certain order.
A set of patches was submitted to the GNU Compiler Collection by Red Hat/Cygnus Solutions in 2003 to include a code generator for it, complete with flags to work around its defects. However, these never worked well enough for it to be usable. It was removed by GCC 4.8 (Sept. 2012).[2]
Several attempts have been made to fix this work: