Longitudinal redundancy check explained

In telecommunication, a longitudinal redundancy check (LRC), or horizontal redundancy check, is a form of redundancy check that is applied independently to each of a parallel group of bit streams. The data must be divided into transmission blocks, to which the additional check data is added.

The term usually applies to a single parity bit per bit stream, calculated independently of all the other bit streams (BIP-8).^{[1] [2]}

This "extra" LRC word at the end of a block of data is very similar to checksum and cyclic redundancy check (CRC).

Optimal rectangular code

While simple longitudinal parity can only detect errors, it can be combined with additional error-control coding, such as a transverse redundancy check (TRC), to correct errors. The transverse redundancy check is stored on a dedicated "parity track".

Whenever any single-bit error occurs in a transmission block of data, such two-dimensional parity checking, or "two-coordinate parity checking",^[3] enables the receiver to use the TRC to detect which byte the error occurred in, and the LRC to detect exactly which track the error occurred in, to discover exactly which bit is in error, and then correct that bit by flipping it.^{[4] [5] [6]}

Pseudocode

International standard ISO 1155^[7] states that a longitudinal redundancy check for a sequence of bytes may be computed in software by the following algorithm:

lrc := 0 for each byte b in the buffer do lrc := (lrc + b) and 0xFF lrc := (((lrc XOR 0xFF) + 1) and 0xFF)

which can be expressed as "the 8-bit two's-complement value of the sum of all bytes modulo 2⁸" (x AND 0xFF is equivalent to x MOD 2<sup>8</sup>).

Other forms

Many protocols use an XOR-based longitudinal redundancy check byte (often called block check character or BCC), including the serial line interface protocol (SLIP, not to be confused with the later and well-known Serial Line Internet Protocol),^[8] the IEC 62056-21 standard for electrical-meter reading, smart cards as defined in ISO/IEC 7816, and the ACCESS.bus protocol.

An 8-bit LRC such as this is equivalent to a cyclic redundancy check using the polynomial x⁸ + 1, but the independence of the bit streams is less clear when looked at in that way.

Notes and References

1. "Reliable link layer protocols".

2. http://www.slideshare.net/angelgdiaz_ut/errors-error-detection-and-error-control-8600677 "Errors, Error Detection, and Error Control: Data Communications and ComputerNetworks: A Business User's Approach"
3. Web site: Chapter1 . 2012-08-20 . 2013-06-13 . https://web.archive.org/web/20130613042831/http://personal.cityu.edu.hk/~dcykcho/dco2310/Chapter7.htm . dead .
4. Gary H. Kemmetmueller."RAM error correction using two dimensional parity checking".
5. Oosterbaan."Longitudinal parity".
6. ftp://mail.im.tku.edu.tw/Prof_Liang/DataComunication&ComputerNetwork/5th%20Edi/Instructor's%20Manual_PDF/9781423903031_IM_PDF/9781423903031_IM_ch06.pdf "Errors, Error Detection, and Error Control"
7. http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=5723 ISO 1155:1978 Information processing -- Use of longitudinal parity to detect errors in information messages
8. ."A Thinwire Protocol for connecting personal computers to the INTERNET".Appendix D: "Serial Line Interface Protocol (SLIP)".