List of Intel CPU microarchitectures explained

The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and .

x86 microarchitectures

Pipeline stages! Max
clock
(MHz)! Process node

1978	8086 (8086, 8088)	2	5	3000 nm
1982	186 (80186, 80188)	2	25
1982	286 (80286)	3	25	1500 nm
1985	386 (80386)	6^[1]	33
1989	486 (80486)	5	100	1000 nm
1993	P5 (Pentium)	5	200	800, 600, 350 nm
1995	P6 (Pentium Pro, Pentium II)	14 (17 with load & store/retire)	450	500, 350, 250 nm
1997	P5 (Pentium MMX)	6	233	350 nm
1999	P6 (Pentium III)	12 (15 with load & store/retire)	1400	250, 180, 130 nm
2000	NetBurst (Pentium 4) (Willamette)	20 unified with branch prediction	2000	180 nm
2002	NetBurst (Pentium 4) (Northwood, Gallatin)		3466	130 nm
2003	Pentium M (Banias, Dothan) Enhanced Pentium M (Yonah)	10 (12 with fetch/retire)	2333	130, 90, 65 nm
2004	NetBurst (Pentium 4, Pentium D) (Prescott)	31 unified with branch prediction	3800	90, 65 nm
2006	Intel Core	12 (14 with fetch/retire)	3000	65 nm
2007	Penryn (die shrink)		3333	45 nm
2008	Nehalem	20 unified (14 without miss prediction)	3600
	Bonnell	16 (20 with prediction miss)	2100
2010	Westmere (die shrink)	20 unified (14 without miss prediction)	3866	32 nm
2011	Saltwell (die shrink)	16 (20 with prediction miss)	2130
	Sandy Bridge	14 (16 with fetch/retire)	4000
2012	Ivy Bridge (die shrink)		4100	22 nm
2013	Silvermont	14–17 (16–19 with fetch/retire)	2670
	Haswell	14 (16 with fetch/retire)	4400
2014	Broadwell (die shrink)		3700	14 nm
2015	Airmont (die shrink)	14–17 (16–19 with fetch/retire)	2640
	Skylake	14 (16 with fetch/retire)	5200
2016	Goldmont	20 unified with branch prediction	2600
2017	Goldmont Plus	20 unified with branch prediction (?)	2800
2018	Palm Cove	14 (16 with fetch/retire)	3200	10 nm
2019	Sunny Cove	12–20 (misprediction)	4100
2020	Tremont	20 unified	3300
	Willow Cove	12 unified	5300
2021		12 unified	5300	14 nm
		12 unified	5500	Intel 7
		20 unified with misprediction penalty	4300
2022	Raptor Cove	12 unified	6200
2023	Redwood Cove			Intel 4, Intel 3
	Crestmont			Intel 4, TSMC N6, Intel 3
2024	Lion Cove			TSMC N3B
	Skymont
Note: Atom/Power efficient microarchitectures are in Italic

8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer.

186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.

286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.

32-bit (IA-32)

i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.

i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.

P5: original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.

P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".

• Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.

• Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have shadow register architecture and speed step technology.

NetBurst:commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit (x86-64)

Core: reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.

• Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.

Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.

• Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.

Sandy Bridge:32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.^[2] First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.

• Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.

Haswell: 22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.

• Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.

Skylake:14 nm microarchitecture, released August 5, 2015.

• Kaby Lake: successor to Skylake, released in August 2016, broke Intel's tick-tock schedule due to delays with the 10 nm process.

• • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)^[3]

• • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)

• Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set.

• Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017

• Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14++ nm process, released in April 2019

• Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019^[4]

• Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020^{[5] [6]}

Palm Cove: Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes the AVX-512 instruction set.^{[7] [8]}

• Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.^[9]

Starting with Cannon Lake, Intel has changed their microarchitecture naming scheme, decoupling core codenames from CPU codenames.^[10]

Sunny Cove:Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms.^[11]

• Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019

• Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.^[12] AVX and more advanced instruction sets are disabled due to the E-core not supporting them.

• Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021^[13]

Cypress Cove: Backport of Sunny Cove to Intel's 14 nm process

• Rocket Lake: Successor to Comet Lake, using Intel's 14++ nm process, released on March 30, 2021^{[14] [15] [16]}

Willow Cove:Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.^[17]

• Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020

Golden Cove:Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.^[18]

• Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),^[19] released on November 4, 2021.^[20] Golden Cove is used in P-cores of Alder Lake processors.^[21]

• Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,^[22] released on January 10, 2023. Introduces AMX.

Raptor Cove:A refresh of Golden Cove with increased L2 and L3 caches and core clocks.

• Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.

• Emerald Rapids: successor to Sapphire Rapids, server- and workstation-only. Fifth-generation Xeon Scalable server processors based on the Intel 7 node.

x86 ULV (Atom)

Bonnell

45 nm, low-power, in-order microarchitecture for use in Atom processors.

• Saltwell: 32 nm shrink of the Bonnell microarchitecture.

Silvermont

22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.

• Airmont: 14 nm shrink of the Silvermont microarchitecture.

Goldmont

14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.^{[23] [24]}

• Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.

Tremont:10 nm Atom microarchitecture iteration after Goldmont Plus.

• Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.^[12]

• Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.

• Elkhart Lake: embedded processors targeted at IoT, released in Q1 2021.

Gracemont

Intel 7 process Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.

• Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.^[21]

• Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

x86 MIC (Many Integrated Core)

Larrabee (cancelled 2010)

multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics.

Xeon Phi

Other microarchitectures

IA-64 (Itanium)

Merced: original Itanium microarchitecture. Used only in the first Itanium microprocessors.

McKinley: enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130 nm version.

Montecito: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-level lockstep execution.

Tukwila: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.

Poulson: Itanium processor featuring an all-new microarchitecture.^[25] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.^[26]

Kittson: the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

Miscellaneous

4004/4040

8008

8080/8085

iAPX 432

80960

80860

XScale

a microarchitecture implementing the ARM architecture instruction set.

Roadmap

Pentium 4 / Core lines

Pentium 4 / Core roadmap

process	Micro-	Code names	Core	Xeon Scalable	Release date	Processors
						Mobile	Desktop	Enthusiast /WS	1P/2P Server	4P/8P Server
180 nm	P6, NetBurst	Willamette				Willamette		Foster	Foster MP
130 nm		Northwood/ Mobile Pentium 4 Banias				Northwood Mobile Banias	Northwood	Northwood-XE	Prestonia Gallatin	Gallatin
90 nm		Prescott Dothan				Dothan	Prescott Smithfield	Prescott 2M-XE Smithfield-XE	Nocona Irwindale Paxville	Potomac Cranford Paxville
65 nm		Cedar Mill Yonah Presler	Core (Yonah only)		Yonah	Cedar Mill Presler	Presler-XE	Dempsey Sossaman	Tulsa
	Core	Merom	Core 2		^[27] ^[28]	Merom	Conroe	Kentsfield	Woodcrest Clovertown	Tigerton
45 nm		Penryn			^[29]	Penryn	Wolfdale	Yorkfield	Harpertown	Dunnington
	Nehalem	Nehalem	Previous^[30] (Core i)		^[31]	Clarksfield	Lynnfield	Bloomfield	Gainestown	Beckton
32 nm		Westmere			^[32] ^[33]	Arrandale	Clarkdale	Gulftown	Westmere-EP	Westmere-EX
	Sandy Bridge	Sandy Bridge	2 (Core i)		^[34]	Sandy Bridge-M	Sandy Bridge	Sandy Bridge-E	Sandy Bridge-EP	^[35]
22 nm		Ivy Bridge	3			Ivy Bridge-M	Ivy Bridge	Ivy Bridge-E ^[36]	Ivy Bridge-EP	Ivy Bridge-EX ^[37]
	Haswell	Haswell	4			Haswell-H Haswell-MB Haswell-ULP/ULX	Haswell-DT ^[38]	Haswell-E	Haswell-EP	Haswell-EX
		Devil's Canyon			2014-06		Haswell-DT	colspan=3
14 nm		Broadwell	5			Broadwell-H Broadwell-U Broadwell-Y	Broadwell-DT	Broadwell-E	Broadwell-EP	Broadwell-EX^[39]
	Skylake	Skylake	6	1	^[40]	Skylake-H Skylake-U Skylake-Y	Skylake-S	Skylake-W Skylake-X^[41]	Skylake-SP (formerly Skylake-EP/-EX)^[42]
		Kaby Lake	7 / 8	2016-10	Kaby Lake-G Kaby Lake-H Kaby Lake-U Kaby Lake-Y	Kaby Lake-S	Kaby Lake-X	colspan="2"
		Coffee Lake	8 / 9		2017-10 ^[43]		Coffee Lake-S		(Xeon E)
		Whiskey Lake	8		2018-08-28		colspan="4" rowspan="2"
		Amber Lake	8 / 10
		Cascade Lake		2				Cascade Lake-AP Cascade Lake-SP
		Comet Lake	10		2019-09	^[44]	Comet Lake-S	Comet Lake-W	colspan="2"
		Cooper Lake		3	2020-06	Cooper Lake-SP
	Cypress Cove^[45] ^[46]	Rocket Lake	11	2021-03			Rocket Lake-W	Rocket Lake (Xeon E)
10 nm	Palm Cove	Cannon Lake	8	2018-05	Cannon Lake-U	colspan=4
	Sunny Cove^[47]	Ice Lake	10	3	2019-09 (mobile) 2021-04 (server)	Ice Lake-U^[48] Ice Lake-Y		Ice Lake-W	^[49]
		Lakefield (hybrid)		^[50]	Lakefield	colspan=4 rowspan=2
	Willow Cove	Tiger Lake	11	2020-09	Tiger Lake-H Tiger Lake-H35 Tiger Lake-UP3 Tiger Lake-UP4
Intel 7	Golden Cove	Alder Lake (hybrid)	12	^[51]	Alder Lake-H Alder Lake-HX Alder Lake-P Alder Lake-U	Alder Lake-S	colspan=3
		Sapphire Rapids		4		Sapphire Rapids-WS	Sapphire Rapids-SP Sapphire Rapids-HBM	Sapphire Rapids-SP
	Raptor Cove	Raptor Lake (hybrid)	13 / 14 / Core Series 1			Raptor Lake-H Raptor Lake-HX Raptor Lake-P Raptor Lake-PX Raptor Lake-U	Raptor Lake-S		Raptor Lake (Xeon E)	rowspan=2
		Emerald Rapids		5		Emerald Rapids-SP
Intel 4	Redwood Cove	Meteor Lake (hybrid)	Core Ultra Series 1		^[52]	Meteor Lake-H Meteor Lake-U	colspan=4
Intel 3		Granite Rapids		6		Granite Rapids-AP Granite Rapids-SP
TSMC N3B	Lion Cove	Lunar Lake (hybrid)	Core Ultra Series 2	2024-09	Lunar Lake-V	colspan=4
		Arrow Lake (hybrid)^[53]				TBA	Arrow Lake-S	colspan=3 rowspan=2
Intel 18A	TBA	Panther Lake (hybrid)	TBA		2025	TBA	?

Atom lines

Atom roadmap^[54]

Fabri- cation process	Micro- archi- tecture	Release date	Processors/SoCs
			MID, smartphone	Tablet	Netbook	Nettop	Embedded	Server	Communication	CE
45 nm	Bonnell	2008	Silverthorne		Diamondville		Tunnel Creek, Stellarton	?	Sodaville
		2010	Lincroft<		-- Moorestown -->	Pineview		Groveland
32 nm	Saltwell	2011	Medfield (Penwell & Lexington), Clover Trail+ (Cloverview)	Clover Trail (Cloverview)	Cedar Trail (Cedarview)		?	Centerton & Briarwood	?	Berryville
22 nm	Silvermont	2013	Merrifield (Tangier),^[55] Slayton, Moorefield (Anniedale)^[56]	Bay Trail-T (Valleyview)	Bay Trail-M (Valleyview)	Bay Trail-D (Valleyview)	Bay Trail-I (Valleyview)	Avoton	Rangeley	?
14 nm	Airmont	2014	Binghamton & Riverton	Cherry Trail-T (Cherryview)^[57]	Braswell^[58]			Denverton	?
	Goldmont ^[59]	2016	Broxton	Willow Trail Apollo Lake	Apollo Lake^[60]			Denverton^[61]
	Goldmont Plus^[62]	2017	?	?	Gemini Lake^[63] Gemini Lake Refresh^[64]			?
10 nm	Tremont^[65]	2020		Lakefield (hybrid)	Lakefield (hybrid)^[66] Elkhart Lake^[67] Jasper Lake^[68]			Jacobsville Parker Ridge^[69] Snow Ridge^[70]
Intel 7	Gracemont^[71]	2021		?	Alder Lake (hybrid)^[72] Raptor Lake (hybrid) Alder Lake-N^[73] ^[74]			?
Intel 4	Crestmont	2023			Meteor Lake (hybrid)	Grand Ridge
TSMC N6					?
Intel 3		2024			?			Sierra Forest
	Skymont	2024			Lunar Lake (hybrid)			?
					Arrow Lake (hybrid)			?
Intel 18A	Darkmont	2025			?			Clearwater Forest

See also

• List of Intel processors - Consumer Computer or non-consumer workstation
• List of AMD CPU microarchitectures
• Marvell Technology Group XScale microarchitecture
• Transient execution CPU vulnerability

External links

• Intel Automated Relational Knowledgebase

Notes and References

1. Rant, Jon; "Extending the Legacy of Leadership: The 80386 Arrives", Intel Corporation, Special 32-Bit Issue Solutions, November/December 1985, page 2
2. Web site: An Update On Our Graphics-related Programs . May 25, 2010.
3. News: Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake. Cutress. Ian. AnandTech. 2018-09-02.
4. Web site: Intel Expands 10th Gen Intel Core Mobile Processor Family, Offering Double Digit Performance Gains. Intel Newsroom. en-US. 2019-08-21.
5. Web site: Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away. Cutress. Ian. AnandTech. 2020-03-18.
6. Web site: Intel Cooper Lake Rationalized Still Launching 1H 2020. Kennedy. Patrick. 2020-03-16. ServeTheHome. en-US. 2020-03-18.
7. Web site: Cutress. Ian. Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review. 2021-04-06. www.anandtech.com.
8. Web site: Palm Cove - Microarchitectures - Intel - WikiChip. en.wikichip.org. en. 2020-01-05.
9. Web site: Intel Fires 10nm Cannon Lake NUC Into Oblivion. Zhiye. Liu. October 31, 2019. Tom's Hardware.
10. Web site: Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips. David. Schor. December 23, 2018. WikiChip Fuse.
11. Web site: Sunny Cove - Microarchitectures - Intel. WikiChip Chips & Semi.
12. Web site: The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU. Ian. Cutress. July 2, 2020. AnandTech.
13. Web site: New Intel Processors Accelerate 5G Network Transformation . Newsroom.intel.com . 2021-04-06 . 2022-05-08.
14. Web site: Intel octet Lake (14nm) Review: Core i911900K, Core i7-11700K, and Core i5-11600K. Ian. Cutress. March 30, 2021. AnandTech.
15. Web site: Intel Confirms Rocket Lake on Desktop for Q1 2021, with PCIe 4.0. AnandTech. 2020-10-07.
16. Web site: Intel's 11th Gen Core Rocket Lake Detailed: Ice Lake Core with Xe Graphics. Ian. Cutress. October 29, 2020. AnandTech.
17. Web site: Willow Cove - Microarchitectures - Intel. WikiChip Chips & Semi.
18. Web site: Cutress. Dr Ian. Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021. 2021-04-10. www.anandtech.com.
19. Web site: Cutress. Dr Ian. Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!. 2021-07-27. www.anandtech.com.
20. Web site: Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids. Ian. Cutress. April 1, 2020. AnandTech.
21. Web site: Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed. 2021-08-19. Cutress. Ian. Frumusanu. Andrei. AnandTech. en. 2021-08-25.
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23. Web site: Intel Software Development Emulator.
24. Web site: "Goldmont"- the sequel to Silvermont Atom?. 23 July 2013 . 2020-03-02.
25. Web site: Intel Plans to change Itanium Micro-Architecture . June 19, 2007 . Anton Shilov . X-bit Labs . 2007-10-05 . dead . https://web.archive.org/web/20071005082838/http://www.xbitlabs.com/news/cpu/display/20070619230827.html . October 5, 2007 .
26. Web site: David Kanter . Poulson: The Future of Itanium Servers . Realworldtech.com . 2011-05-18 . 2022-05-08.
27. Web site: Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing.
28. Web site: Intel Unveils World's Best Processor.
29. Web site: Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology.
30. Web site: ARK Your source for information on Intel products. 2013-05-30. Intel. https://web.archive.org/web/20130530074015/http://ark.intel.com/. 2013-05-30. unfit. 2013-05-30.
31. Web site: Intel Launches Fastest Processor on the Planet. www.intel.com.
32. Web site: Intel 32nm Technology. Mark Bohr (Intel Senior Fellow, Logic Technology Development). 2009-02-10.
33. Web site: Intel - Data Center Solutions, IoT, and PC Innovation. Intel.
34. Web site: Intel Sandy Bridge chip coming January 5.
35. Web site: Intel Ivy Bridge CPU Range Complete by Next Year. Sebastian. Pop. 9 April 2012 .
36. Web site: Ivy Bridge-E delayed until second half of 2013. 19 March 2012 .
37. Web site: Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven. 9 April 2012.
38. Web site: Leaked specifications of Haswell GT1/GT2/GT3 IGP . Tech News Pedia . 2012-05-20 . 2014-02-25 . https://web.archive.org/web/20120919234611/http://technewspedia.com/leaked-specifications-of-haswell-gt1gt2gt3-igp/ . 2012-09-19 . dead .
39. Web site: Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru. www.kitguru.net.
40. Web site: The wait for Skylake is almost over, first desktop chips likely to hit August 5. 6 July 2015.
41. Web site: Mujtaba. Hassan. Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June. wccftech.com. 25 April 2017 . 2 May 2017.
42. Web site: Windeck. Christof. Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer". heise.de. 30 April 2017 . 2 May 2017.
43. Web site: Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de.
44. Web site: Comet Lake-U: 15-Watt-CPUs für Notebook-CPUs mit sechs Kernen. online. heise. c't Magazin. 21 August 2019 . de. 2019-08-21.
45. Web site: Intel's 11th Gen Processor (Rocket Lake-S) Architecture Detailed. 2020-10-29. Intel Newsroom. en-US.
46. Web site: Intel "Rocket Lake-S": 11. Core-i-Generation mit mehr Rechenleistung pro Takt. 2020-10-29. heise online. 29 October 2020 . de.
47. Web site: Intel unveils a new architecture for 2019: Sunny Cove. Bright. Peter. 2018-12-12. Ars Technica. en-us. 2018-12-12.
48. Web site: Ice Lake Processor Family. Intel. en. 2018-12-12.
49. Web site: Server-CPUs: Cooper Lake und Ice Lake nutzen gleichen Sockel - Golem.de. www.golem.de. de-DE. 2019-04-23.
50. News: Intel Launches Lakefield Hybrid Processors: Uncompromised PC Experiences for Innovative Form-Factors . 2020-06-10 . TechPowerUp . 2024-10-04.
51. Web site: Intels neuer Anlauf mit "Sunny Cove", Gen-11-GPU und Chiplets. 2018-12-12. heise online. 12 December 2018 . de.
52. Web site: Intel Innovation 2023: Empowering Developers to Bring AI Everywhere .
53. News: Intel Client & Server CPU Roadmap Updates: Meteor Lake In 2023, 20A & 18A Powered Xeons & Core Chips Beyond 2024. 2022-02-17. Wccftech. 17 February 2022. Mujtaba . Hassan .
54. Web site: Intel's Silvermont Architecture Revealed: Getting Serious About Mobile. AnandTech.
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