IP-XACT explained

IP-XACT, also known as IEEE 1685,^[1] is an XML format that defines and describes individual, re-usable electronic circuit designs (individual pieces of intellectual property, or IPs) to facilitate their use in creating integrated circuits (i.e. microchips). IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through tools^[2] and evolving into an IEEE standard.

The goals of the standard are

• to ensure delivery of compatible component descriptions, such as IPs, from multiple component vendors,
• to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),
• to describe configurable components using metadata, and
• to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators).

Approved as IEEE 1685-2009 on December 9, 2009, published on February 18, 2010.^[3] Superseded by IEEE 1685-2014. IEEE 1685-2009 was adopted as IEC 62014-4:2015. In June 2023, the supplemental material for standard IEEE 1685-2022 IP-XACT was approved by Accellera.^[4]

Overview

Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.

All documents will have the following basic titular attributes spirit:vendor, spirit:library, spirit:name, spirit:version.

A document typically represents one of:

• bus specification, giving its signals and protocol etc.;
• leaf IP block data sheet;
• or a hierarchic component wiring diagram that describes a sub-system by connecting up or abstracting other components made up of spirit:componentInstance and spirit:interconnection elements.

For each port of a component there will be a spirit:busInterface element in the document. This may have a spirit:signalMapthat gives the mapping of the formal net names in the interface to the names used in a corresponding formal specification of the port.A simple wiring tool will use the signal map to know which net on one interface to connect to which net on another instanceof the same formal port on another component.

There may be various versions of a component referenced in the document, each as a spirit:view element, relating to different versions of a design: typical levels are gate-level, RTL and TLM.Each view typically contains a list of filenames as a spirit:fileSet that implement the design at that level of abstraction in appropriate language, like Verilog,C++ or PSL.

Non-functional data present includes the programmer's view with a list of spirit:register declarations inside a spirit:memoryMap or spirit:addressBlock.

Supporting companies and software

• Arteris ^[5] - Magillem Connectivity,^[6] Magillem Registers,^[7] CSRCompiler^[8] and FlexNoC5^[9]
• Cadence - JasperGold ^[10] and Interconnect Workbench (IWB) ^[11]
• Synopsys, Inc ^[12]
• Agnisys ^[13]
• Defacto Technologies ^[14]
• EDAUtils ^[15]
• Magillem (now part of Arteris) ^[16]
• Semifore (now part of Arteris) ^[17]
• Xilinx (now part of AMD)
• Lattice

See also

• SystemRDL

References

• Book: 10.1109/IEEESTD.2023.10054520. 1685-2022 - IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2023. 978-1-5044-9448-9.
• Book: 10.1109/IEEESTD.2014.6898803. 1685-2014 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2014. 978-0-7381-9226-0.
• Book: 1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows. 10.1109/IEEESTD.2010.5417309. 2010. 978-0-7381-6160-0.
  • Book: 10.1109/IEEESTD.2015.7066223. 2015. 978-2-8322-2265-2. IEEE/IEC International Standard - IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows.

Further reading

• SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform
• 10.1109/MDT.2006.104. Standards: The P1685 IP-XACT IP Metadata Standard. IEEE Design & Test of Computers. 23. 4. 316–317. April 2006. Berman . V.. 206459094.
• 10.1145/1403375.1403386. Industrial IP integration flows based on IP-XACT™ standards. Proceedings of the conference on Design, automation and test in Europe. DATE'08. 32–37. 2008. Kruijtzer . W. . Vaumorin . E. . Van Der Wolf . P. . De Kock . E. . Stuyt . J. . Ecker . W. . Mayer . A. . Hustin . S. . Amerijckx . C. . De Paoli . S. . 978-3-9810801-3-1. 10.1.1.455.8801 .

External links

• IEEE 1685-2022
• IP-XACT at Accellera
  • XML Schema at Accellera
  • BusDefs at Accellera

Notes and References

1. Web site: IEEE Standards Association . 2023-10-27 . IEEE Standards Association . en.
2. http://accellera.org/activities/working-groups/ip-xact/ IP-XACT Working Group
3. IEEE 1685-2009,
4. Web site: IP-XACT . 2023-10-27 . www.accellera.org.
5. Web site: Arteris . 2023-10-27 . en-US.
6. Web site: Magillem Connectivity – Arteris . 2023-10-27 . en-US.
7. Web site: Magillem Registers – Arteris . 2023-10-27 . en-US.
8. Web site: CSRCompiler – Arteris . 2023-10-27 . en-US.
9. Web site: FlexNoC 5 Interconnect IP – Arteris . 2023-10-27 . en-US.
10. https://www.cadence.com/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/jaspergold-control-and-status-register-app.html Cadence's JasperGold Control and Status Register App
11. https://community.arm.com/developer/ip-products/system/b/soc-design-blog/posts/the-future-of-tooling-from-ip-configuration-to-soc-verification Cadence Interconnect Workbench
12. https://www.synopsys.com/designware-ip/ip-reuse-tool.html Synopsys, Inc
13. https://www.agnisys.com/products/idesignspec-uvm-register-generator/ Agnisys IDesignSpec
14. https://www.defactotech.com/products-solutions/soc-integration-at-rtl/ Defacto SoC Compiler
15. http://www.edautils.com/ip-xact.html EDAUtils
16. http://www.magillem.com/ip-xact-ieee-1685/ Magillem Design Services
17. http://www.semifore.com/standards-support/ Semifore, Inc