IBM Scalable POWERparallel explained
Scalable POWERparallel (SP) is a series of supercomputers from IBM. SP systems were part of the IBM RISC System/6000 (RS/6000) family, and were also called the RS/6000 SP. The first model, the SP1, was introduced in February 1993, and new models were introduced throughout the 1990s until the RS/6000 was succeeded by eServer pSeries in October 2000. The SP is a distributed memory system, consisting of multiple RS/6000-based nodes interconnected by an IBM-proprietary switch called the High Performance Switch (HPS). The nodes are clustered using software called PSSP, which is mainly written in Perl.
Computer scientist Marc Snir was awarded the Seymour Cray Computer Engineering Award by the Institute of Electrical and Electronics Engineers in 2013 for his contributions to supercomputing, which included his work on the SP.[1]
Notable systems
Nodes
POWER1-based
width=120 | Model | width=100 | - of CPUs
| width=100 | CPU | width=100 | CPU MHz | width=100 | Cache | width=100 | Memory | width=100 | Introduced | width=100 | Discontinued |
---|
SP1 | 1 | POWER1++ | 62.5 | None | 64 to 256 MB | 1993-02-02 | 1994-12-16 |
|
POWER2-based
width=120 | Model | width=100 | - of CPUs
| width=100 | CPU | width=100 | CPU MHz | width=100 | L2 Cache | width=100 | Memory | width=100 | Introduced | width=100 | Discontinued |
---|
Thin Node | 1 | POWER2 | 66 | ? | 64 to 512 MB | 1994-04-06[4] | 1996-07-26[5] |
Thin Node 2 | ? | 64 to 512 MB | 1995-02-07[6] | 1997-06-27[7] |
Wide Node | ? | 64 MB to 2 GB | 1994-04-06 | 1996-07-26 |
77MHz Wide Node | 77 | ? | 64 MB to 2 GB | 1995-08-22[8] | 1997-06-27 |
|
PowerPC 604-based
width=120 | Model | width=100 | - of CPUs
| width=100 | CPU | width=100 | CPU MHz | width=100 | Cache | width=100 | Memory | width=100 | Introduced | width=100 | Discontinued |
---|
High 1 | 2, 4, 6, 8 | PowerPC 604 | 112 | ? | ? | 1996-07-23 | 1998-01-08 |
High 2 | PowerPC 604e | 200 | ? | ? | 1997-08-26 | 1998-04-21 |
332 Thin | 2, 4 | 332 | ? | ? | 1998-04-21 | 2000-12-29 |
332 Wide | ? | ? |
|
P2SC-based
Model | - of CPUs
| CPU | CPU MHz | Cache | Memory | Introduced | Discontinued |
---|
160 Thin | 1 | P2SC | 160 | ? | ? | 1997-10-06 | 1998-04-21 |
Thin P2SC | 120 | ? | ? | 1996-10-08 |
Wide P2SC | 135 | ? | ? |
|
POWER3-based
Model | - of CPUs
| CPU | CPU MHz | L2 Cache | Memory | Introduced | Discontinued |
---|
POWER3 High | 2, 4, 6, 8 | POWER3 | 222 | ? | ? | 1999-09-13 | 2000-12-29 |
POWER3 High | POWER3-II | 375 | ? | ? | 2000-07-18 | 2002-12-27 |
POWER3 Thin | 1, 2 | POWER3 | 200 | ? | ? | 1999-09-01 | 2000-06-30 |
POWER3 Thin | POWER3-II | 375 | ? | ? | 2000-02-07 | 2003-04-08 |
POWER3 Thin | 450 | ? | ? | 2002-01-22 |
POWER3 Wide | 1, 2 | POWER3 | 200 | ? | ? | 1999-02-01 | 2000-06-30 |
POWER3 Wide | 2, 4 | POWER3-II | 375 | ? | ? | 2000-02-07 | 2003-04-08 |
POWER3 Wide | 2, 4 | 450 | ? | ? | 2002-01-22 |
|
See also
External links
Notes and References
- Web site: Marc Snir: 2013 Seymour Cray Award Recipient . IEEE Computer Society . https://web.archive.org/web/20140326031819/http://www.computer.org/portal/web/awards/marc-snir . 2014-03-26 . dead.
- Web site: SP2/512 . TOP500 Supercomputer Sites . 2 January 2019.
- Web site: Seaborg - SP Power3 375 MHz 16 way . TOP500 Supercomputer Sites . 2 January 2019.
- IBM Announcement Letter ZG94-0159: IBM Scalable POWERparallel Systems 9076 SP2 and Enhancements for SP1
- IBM Announcement 996-181: Hardware Withdrawal: RISC System/6000 SP POWERquery and Selected Models and Features -- Replacements Available
- IBM Announcement Letter ZG95-0145: 9076 POWERparallel SP2 Models 204, 304, 3B4, and 404
- IBM Announcement Letter 997-078: Hardware Withdrawal: Selected RS/6000 Models and Features -- Replacements Available
- IBM Announcement Letter ZG95-0364: RISC SYSTEM/6000 SP 77MHz Wide Models, 2AX Models, and Enhancements