| P6 | |
| Slowest: | 150[1] |
| Fastest: | 1.40 |
| Slow-Unit: | MHz |
| Fsb-Slowest: | 66 |
| Fsb-Fastest: | 133 |
| Fsb-Slow-Unit: | MHz |
| Fsb-Fast-Unit: | MHz |
| L1cache: | Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache) Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache) |
| L2cache: | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
| Arch: | x86-16, IA-32 |
| Extensions: | MMX (Pentium II/III/M) SSE (Pentium III/M) SSE2 (Pentium M) |
| Microarch: | P6 |
| Transistors1: | 5.5M 500 nm |
| Transistors2: | 7.5M 350 nm |
| Transistors3: | 7.5M 250 nm (B0, B1) |
| Transistors4: | 9.5M 250 nm (B0, C0) |
| Transistors5: | 19M 250 nm (B0) |
| Transistors6: | 28M 180 nm (A1, A2, B0, C0, D0) |
| Transistors7: | 44M 130 nm (A1, B1, C1, D0) |
| Numcores: | 1 |
| Sock1: | Socket 8 |
| Sock2: | Slot 1 |
| Sock3: | Socket 370 |
| Sock4: | Socket 479 |
| Model: | Pentium Pro Series |
| Model1: | Celeron II Series |
| Model2: | Pentium II Series |
| Model3: | Pentium II Xeon Series |
| Model4: | Celeron III Series |
| Model5: | Pentium III Series |
| Model6: | Pentium III Xeon Series |
| Predecessor: | P5 |
| Successor: | NetBurst |
| Support Status: | Unsupported |
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686.[2] It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.
P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).
FeaturesP6 processors dynamically translate IA-32 instructions into sequences of buffered RISC-like micro-operations, then analyze and reorder the micro-operations to detect parallelizable operations that may be issued to more than one execution unit at once.[3] The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique, though the NexGen Nx586, introduced in 1994, did so earlier.
Other features first implemented in the x86 space in the P6 core include:
See main article: Pentium M.
| P6 Pentium M | |
| Created: | March 12, 2003 |
| Model: | A100 Series |
| Model1: | EP80579 Series |
| Model2: | Celeron M Series |
| Model3: | Pentium M Series |
| Cores: | 1 |
| Transistors: | 77M 130 nm (B1, B2) |
| Transistors1: | 144M 90 nm (B0, C0) |
| Transistors2: | 151M 65 nm (C0, D0) |
| Clock: | 600 MHz to 2.26 GHz |
| L1cache: | 64KB (32 KB I Cache + 32 KB D cache) |
| L2cache: | 512 KB to 2048 KB |
| Fsb: | 400 MT/s to 533 MT/s |
| Arch: | x86-16, IA-32 |
| Extensions: | MMX, SSE, SSE2 |
| Microarch: | P6 |
| Socket: | Socket 479 |
| Predecessor: | NetBurst |
| Successor: | Enhanced Pentium M |
| Support Status: | Unsupported |
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. NetBurst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors without significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life. Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M.
Design Overview[6]
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.
The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.[7] Windows 8 and later also refuses to boot on these processors for the same reason, as they specifically require PAE support to run properly.[8]
See main article: Yonah (microprocessor).
| P6 Enhanced Pentium M | |
| Created: | 2006 |
| Model: | Celeron M Series |
| Model1: | Pentium Dual-Core Series |
| Model2: | Core Solo Series |
| Model3: | Core Duo Series |
| Model4: | Xeon LV Series |
| Cores: | 1-2 |
| Transistors: | 151M 65 nm (C0, D0) |
| Clock: | 1.06 GHz to 2.33 GHz |
| L1cache: | 64 KB |
| L2cache: | 1 MB to 2 MB 2 MB (Xeon) |
| Fsb: | 533 MT/s to 667 MT/s |
| Arch: | x86-16, IA-32 |
| Extensions: | MMX, SSE, SSE2, SSE3 |
| Microarch: | P6 |
| Socket: | Socket M |
| Predecessor: | Pentium M |
| Successor: | Intel Core |
| Support Status: | Unsupported |
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the Pentium M's shortcomings by adding:
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
On July 27, 2006, the Core microarchitecture, a derivative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon, Pentium and Celeron brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and later Intel microarchitectures featuring an integrated memory controller and a QPI or DMI bus for communication with the rest of the system. Improvements relative to the Intel Core processors were:
While all these chips are technically derivatives of the Pentium Pro, the architecture has gone through several radical changes since its inception.[9]