The High-Level Shader Language[1] or High-Level Shading Language[2] (HLSL) is a proprietary shading language developed by Microsoft for the Direct3D 9 API to augment the shader assembly language, and went on to become the required shading language for the unified shader model of Direct3D 10 and higher.
HLSL is analogous to the GLSL shading language used with the OpenGL standard. It is very similar to the Nvidia Cg shading language, as it was developed alongside it. Early versions of the two languages were considered identical, only marketed differently.[3] HLSL shaders can enable profound speed and detail increases as well as many special effects in both 2D and 3D computer graphics.
HLSL programs come in six forms: pixel shaders (fragment in GLSL), vertex shaders, geometry shaders, compute shaders, tessellation shaders (Hull and Domain shaders), and ray tracing shaders (Ray Generation Shaders, Intersection Shaders, Any Hit/Closest Hit/Miss Shaders). A vertex shader is executed for each vertex that is submitted by the application, and is primarily responsible for transforming the vertex from object space to view space, generating texture coordinates, and calculating lighting coefficients such as the vertex's normal, tangent, and bitangent vectors. When a group of vertices (normally 3, to form a triangle) come through the vertex shader, their output position is interpolated to form pixels within its area; this process is known as rasterization.
Optionally, an application using a Direct3D 10/11/12 interface and Direct3D 10/11/12 hardware may also specify a geometry shader. This shader takes as its input some vertices of a primitive (triangle/line/point) and uses this data to generate/degenerate (or tessellate) additional primitives or to change the type of primitives, which are each then sent to the rasterizer.
D3D11.3 and D3D12 introduced Shader Model 5.1[4] and later 6.0.[5]
GPUs listed are the hardware that first supported the given specifications. Manufacturers generally support all lower shader models through drivers. Note that games may claim to require a certain DirectX version, but don't necessarily require a GPU conforming to the full specification of that version, as developers can use a higher DirectX API version to target lower-Direct3D-spec hardware; for instance DirectX 9 exposes features of DirectX7-level hardware that DirectX7 did not, targeting their fixed-function T&L pipeline.
Pixel shader version | 1.0 | 1.1 | 1.21.3[6] | 1.4 | 2.0[7] | 2.0a[8] | 2.0b[9] | 3.0[10] | 4.0[11] 4.1[12] 5.0[13] | |
---|---|---|---|---|---|---|---|---|---|---|
Dependent texture limit | 4 | 4 | 4 | 6 | 8 | Unlimited | 8 | Unlimited | Unlimited | |
Texture instruction limit | 4 | 4 | 4 | 6 * 2 | 32 | Unlimited | Unlimited | Unlimited | Unlimited | |
Arithmetic instruction limit | 8 | 8 | 8 | 8 * 2 | 64 | Unlimited | Unlimited | Unlimited | Unlimited | |
Position register | ||||||||||
Instruction slots | 8 | 8 + 4 | 8 + 4 | (8 + 6) * 2 | 64 + 32 | 512 | 512 | ≥ 512 | ≥ 65536 | |
Executed instructions | 8 | 8 + 4 | 8 + 4 | (8 + 6) * 2 | 64 + 32 | 512 | 512 | 65536 | Unlimited | |
Texture indirections | 4 | 4 | 4 | 4 | 4 | Unlimited | 4 | Unlimited | Unlimited | |
Interpolated registers | 2 + 4 | 2 + 4 | 2 + 4 | 2 + 6 | 2 + 8 | 2 + 8 | 2 + 8 | 10 | 32 | |
Instruction predication | ||||||||||
Index input registers | ||||||||||
Temp registers | 2 | 2 + 4 | 3 + 4 | 6 | 12 to 32 | 22 | 32 | 32 | 4096 | |
Constant registers | 8 | 8 | 8 | 8 | 32 | 32 | 32 | 224 | 16×4096 | |
Arbitrary swizzling | ||||||||||
Gradient instructions | ||||||||||
Loop count register | ||||||||||
Face register (2-sided lighting) | ||||||||||
Dynamic flow control | (24) | (64) | ||||||||
Bitwise Operators | ||||||||||
Native Integers |
"32 + 64" for Executed Instructions means "32 texture instructions and 64 arithmetic instructions."
Vertex shader version | 1.0 | 1.1[14] !2.0 | 2.0a | 3.0 | 4.0 4.1 5.0 | ||
---|---|---|---|---|---|---|---|
| 128 | 128 | 256 | 256 | ≥ 512 | ≥ 65536 | |
Max # of instructions executed | 128 | 128 | 1024 | 65536 | 65536 | Unlimited | |
Instruction predication | |||||||
Temp registers | 12 | 12 | 12 | 16 | 32 | 4096 | |
| ≥ 96 | ≥ 96 | ≥ 256 | 256 | ≥ 256 | 16×4096 | |
Address register | |||||||
Static flow control | |||||||
Dynamic flow control | |||||||
Dynamic flow control depth | 24 | 24 | 64 | ||||
Vertex texture fetch | |||||||
| 4 | 128 | |||||
Geometry instancing support | |||||||
Bitwise operators | |||||||
Native integers |