HDL simulators are software packages that simulate expressions written in one of the hardware description languages, such as VHDL, Verilog, SystemVerilog.
This page is intended to list current and historical HDL simulators, accelerators, emulators, etc.
| Simulator name | Author/company | Languages | Description | |
|---|---|---|---|---|
| Active-HDL / Riviera-PRO | VHDL-1987,-1993,-2002,-2008,-2019 V1995, V2001, V2005, SV2009, SV2012, SV2017 | Active-HDL is Aldec's Windows-based simulator with complete HDL graphical entry and verification environment aimed at FPGA and SoC FPGA applications. Riviera-PRO is Aldec's Windows/Linux-based simulator with complete verification environment aimed at FPGA, SoC FPGA and ASIC applications. Both Aldec simulators are the most cost-effective simulators in the industry, with advanced debugging capabilities and high-performance simulation engines, supports advanced verification methodologies such as assertion based verification and UVM. Aldec simulators have the complete VHDL-2008 implementation and the first to offer VHDL-2019 features. Aldec has the most cost-effective commercial simulator in the industry. | ||
| Aeolus-DS | Huada Empyrean Software Co., Ltd | V2001 | Aeolus-DS is a part of Aeolus simulator which is designed to simulate mixed signal circuit. Aeolus-DS supports pure Verilog simulation. | |
| HiLo | Teradyne | Used in 1980s. | ||
| Incisive Enterprise Simulator ('big 3') | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. It also provides support for the e verification language, and a fast SystemC simulation kernel. | ||
| ISE Simulator | VHDL-93, V2001 | Xilinx's simulator comes bundled with the ISE Design Suite. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs. | ||
| Metrics Cloud Simulator | Metrics Technologies | SV2012 | SystemVerilog simulator used on the Metrics cloud platform. Includes all the standard features of a modern SystemVerilog simulator including debug, APIs, language and testbench support. | |
| ModelSim / Questa ('big 3') | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. In 2003, ModelSim 5.8 was the first simulator to begin supporting features of the Accellera SystemVerilog 3.0 standard.[1] In 2005 Mentor introduced Questa to provide high performance Verilog and SystemVerilog simulation and expand Verification capabilities to more advanced methodologies such as Assertion Based Verification and Functional Coverage. Today Questa is the leading high performance SystemVerilog and Mixed simulator supporting a full suite of methodologies including industry standard OVM and UVM. ModelSim is still the leading simulator for FPGA design. | ||
| MPSim | Axiom Design Automation | V2001, V2005, SV2005, SV2009 | MPsim is a fast compiled simulator with full support for Verilog, SystemVerilog and SystemC. It includes Designer, integrated Verilog and SystemVerilog debugging environment and has built-in support for multi-cpu simulation. | |
| PureSpeed | Frontline | V1995 | The first Verilog simulator available on the Windows OS. The simulator had a cycle-based counterpart called 'CycleDrive'. FrontLine was sold to Avant! in 1998, which was later acquired by Synopsys in 2002. Synopsys discontinued Purespeed in favor of its well-established VCS simulator. | |
| Quartus II Simulator (Qsim) | VHDL-1993, V2001, SV2005 | Altera's simulator bundled with the Quartus II design software in release 11.1 and later. Supports Verilog, VHDL and AHDL. | ||
| SILOS | V2001 | As one of the low-cost interpreted Verilog simulators, Silos III, from SimuCad, enjoyed great popularity in the 1990s. With Silvaco's acquisition of SimuCad, Silos is part of the Silvaco EDA tool suite. | ||
| SIMILI VHDL | Symphony EDA | VHDL-1993 | Another low-cost VHDL simulator with graphical user interface and integrated waveform viewer. Their web site was not updated for quite some time now. You can no longer purchase the software. The free version does work but you have to request a license via email. | |
| SMASH | V1995, V2001, VHDL-1993 | SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms. | ||
| Speedsim | V1995 | Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel. | ||
| Super-FinSim | Fintronic | V2001 | This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance. | |
| TEGAS / Texsim | TEGAS/CALMA/GE | TDL (Tegas Design Language) | First described in 1972 paper, used in 1980s by ASIC vendors such as LSI Logic, GE. | |
| VCS ('big 3') | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, which was acquired by ViewLogic Systems in 1994. ViewLogic was subsequently acquired by Synopsys in 1997. VCS has been in continuous active development, and pioneered compiled-code simulation, native testbench and SystemVerilog support, and unified compiler technologies. Today, VCS provides comprehensive support for all functional verification methodologies and languages (including VHDL, Verilog, SystemVerilog, Verilog AMS, SystemC, and C/C++), and advanced simulation technologies including native low power, x-propagation, unreachability analysis, and fine-grained parallelism. | ||
| Verilogger Extreme / Pro | SynaptiCAD | V2001, V1995 | Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro. | |
| Verilog-XL | V1995 | The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators. | ||
| Veritak | Sugawara Systems | V2001 | It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution. | |
| Xilinx Simulator (XSIM) | VHDL-1993,-2002 (subset),-2008 (subset),[2] V2001, V2005, SV2009, SV2012, SV2017 | Xilinx Simulator (XSIM) comes as part of the Vivado design suite. It is a compiled-language simulator that supports mixed language simulation with Verilog, SystemVerilog, VHDL and SystemC language. It supports standard debugging tool such as step through code, breakpoints, cross-probing, value probes, call stack and local variable Window. The waveform viewer in Xilinx Simulator supports virtual bus, signal grouping, analog view & protocol viewing features. It also supports UVM 1.2 and functional coverage for advanced verification. It supports both GUI and batch mode via TCL script and allows simulation of encrypted IPs. Xilinx Simulator supports SystemVerilog Direct Programming Interface (DPI) and Xilinx simulator interface (XSI) to connect C/C++ model with Xilinx simulator. | ||
| Z01X | WinterLogic (acquired by Synopsys 2016) | V2001, SV2005 | Developed as a fault simulator but can also be used as a logic simulator. | |
Some commercial proprietary simulators (such as ModelSim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are sometimes offered free of charge.
| Simulator name | License | Author/company | Supported languages | Description | |
|---|---|---|---|---|---|
| Cascade | BSD | VMware Research | V2005 (large subset) | Just-in-Time Verilog simulator and compiler for FPGAs allowing to instantly run both synthesizable and unsynthesizable Verilog on hardware | |
| CVC | Perl style artistic license [3] | Tachyon Design Automation | V2001, V2005 | CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. | |
| GPL Cver | GPL | Pragmatic C Software | V1995, minimal V2001 | This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions. | |
| GPL2+ | Stephen Williams | V1995, V2001, V2005, limited SV2005/SV2009/SV2012 | Also known as iverilog. Good support for Verilog 2005, including generate statements and constant functions. | ||
| Isotel Mixed Signal & Domain Simulation | GPL | ngspice, Yosys communities and Isotel | V2005 | Open-source mixed signal ngspice simulator in combination with verilog synthesis software called Yosys and Isotel extension for embedded C/C++ (or other) co-simulation. | |
| LIFTING | A. Bosio, G. Di Natale (LIRMM) | V1995 | LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. | ||
| OSS CVC | Perl style artistic license | Tachyon Design Automation | V2001, V2005 | CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. Source code is available under a Perl style artistic license. | |
| TkGate | GPL2+ | Jeffery P. Hansen | V1995 | Event driven digital circuit editor and simulator with tcl/tk GUI based on Verilog. Includes Verilog simulator Verga. | |
| GPL3 | Veripool | V1995, V2001, V2005, SV2005, SV2009, SV2012, SV2017, SV2023 | Verilator is a very high speed open-source simulator that compiles Verilog to multithreaded C++/SystemC. Verilator previously required that testbench code be written as synthesizable RTL, or as a C++ or SystemC testbench, because Verilator did not support behavioral Verilog. These are now supported. | ||
| Verilog Behavioral Simulator (VBS) | GPL | Lay H. Tho and Jimen Ching | V1995 | Supports functions, tasks and module instantiation. It has a few features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements. | |
| VeriWell | GPL2 | Elliot Mednick | V1995 | This simulator used to be proprietary, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364–1995. | |
| Simulator name | License | Author/company | Supported languages | Description | |
|---|---|---|---|---|---|
| FreeHDL | GPL2+ | Edwin Naroska | VHDL-1987, VHDL-1993 | A project to develop a free, open source, VHDL simulator | |
| GHDL | GPL2+ | Tristan Gingold | VHDL-1987, VHDL-1993, VHDL-2002, partial VHDL-2008, partial VHDL-2019 | GHDL is a complete VHDL simulator, using the GCC technology. | |
| NVC | GPL-3.0-or-later | Nick Gasson and contributors | VHDL-1993, VHDL-2002, VHDL-2008, partial VHDL-2019[4] | NVC is a GPLv3 VHDL compiler and simulator. It is available for various distributions of Linux, macOS, Windows (via Cygwin or MSYS2), and OpenBSD. |
| Tag | Description | |
|---|---|---|
| V1995 | IEEE 1364-1995 Verilog | |
| V2001 | IEEE 1364-2001 Verilog | |
| V2005 | IEEE 1364-2005 Verilog | |
| SV2005 | IEEE 1800-2005 SystemVerilog | |
| SV2009 | IEEE 1800-2009 SystemVerilog | |
| SV2012 | IEEE 1800-2012 SystemVerilog | |
| SV2017 | IEEE 1800-2017 SystemVerilog | |
| SV2023 | IEEE 1800-2023 SystemVerilog | |
| VHDL-1987 | IEEE 1076-1987 VHDL | |
| VHDL-1993 | IEEE 1076-1993 VHDL | |
| VHDL-2002 | IEEE 1076-2002 VHDL | |
| VHDL-2008 | IEEE 1076-2008 VHDL | |
| VHDL-2019 | IEEE 1076-2019 VHDL |