Linear-feedback shift register explained

In computing, a linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state.

The most commonly used linear function of single bits is exclusive-or (XOR). Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value.

The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits that appears random and has a very long cycle.

Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common.

The mathematics of a cyclic redundancy check, used to provide a quick check against transmission errors, are closely related to those of an LFSR.[1] In general, the arithmetics behind LFSRs makes them very elegant as an object to study and implement. One can produce relatively complex logics with simple building blocks. However, other methods, that are less elegant but perform better, should be considered as well.

Fibonacci LFSRs

The bit positions that affect the next state are called the taps. In the diagram the taps are [16,14,13,11]. The rightmost bit of the LFSR is called the output bit, which is always also a tap. To obtain the next state, the tap bits are XOR-ed sequentially; then, all bits are shifted one place to the right, with the rightmost bit being discarded, and that result of XOR-ing the tap bits is fed back into the now-vacant leftmost bit. To obtain the pseudorandom output stream, read the rightmost bit after each state transition.

The sequence of numbers generated by an LFSR or its XNOR counterpart can be considered a binary numeral system just as valid as Gray code or the natural binary code.

The arrangement of taps for feedback in an LFSR can be expressed in finite field arithmetic as a polynomial mod 2. This means that the coefficients of the polynomial must be 1s or 0s. This is called the feedback polynomial or reciprocal characteristic polynomial. For example, if the taps are at the 16th, 14th, 13th and 11th bits (as shown), the feedback polynomial is

x16+x14+x13+x11+1.

The "one" in the polynomial does not correspond to a tap – it corresponds to the input to the first bit (i.e. x0, which is equivalent to 1). The powers of the terms represent the tapped bits, counting from the left. The first and last bits are always connected as an input and output tap respectively.

The LFSR is maximal-length if and only if the corresponding feedback polynomial is primitive over the Galois field GF(2).[3] [4] This means that the following conditions are necessary (but not sufficient):

Tables of primitive polynomials from which maximum-length LFSRs can be constructed are given below and in the references.

There can be more than one maximum-length tap sequence for a given LFSR length. Also, once one maximum-length tap sequence has been found, another automatically follows. If the tap sequence in an n-bit LFSR is, where the 0 corresponds to the x0 = 1 term, then the corresponding "mirror" sequence is . So the tap sequence has as its counterpart . Both give a maximum-length sequence.

An example in C is below:

  1. include

unsigned lfsr_fib(void)

If a fast parity or popcount operation is available, the feedback bit can be computed more efficiently as the dot product of the register with the characteristic polynomial:

If a rotation operation is available, the new state can be computed as

This LFSR configuration is also known as standard, many-to-one or external XOR gates. The alternative Galois configuration is described in the next section.

Example in Python

A sample python implementation of a similar (16 bit taps at [16,15,13,4]) Fibonacci LFSR would be

start_state = 1 << 15 | 1lfsr = start_stateperiod = 0

while True: # taps: 16 15 13 4; feedback polynomial: x^16 + x^15 + x^13 + x^4 + 1 bit = (lfsr ^ (lfsr >> 1) ^ (lfsr >> 3) ^ (lfsr >> 12)) & 1 lfsr = (lfsr >> 1) | (bit << 15) period += 1 if lfsr

start_state: print(period) break

Where a register of 16 bits is used and the xor tap at the fourth, 13th, 15th and sixteenth bit establishes a maximum sequence length.

Galois LFSRs

Named after the French mathematician Évariste Galois, an LFSR in Galois configuration, which is also known as modular, internal XORs, or one-to-many LFSR, is an alternate structure that can generate the same output stream as a conventional LFSR (but offset in time).[5] In the Galois configuration, when the system is clocked, bits that are not taps are shifted one position to the right unchanged. The taps, on the other hand, are XORed with the output bit before they are stored in the next position. The new output bit is the next input bit. The effect of this is that when the output bit is zero, all the bits in the register shift to the right unchanged, and the input bit becomes zero. When the output bit is one, the bits in the tap positions all flip (if they are 0, they become 1, and if they are 1, they become 0), and then the entire register is shifted to the right and the input bit becomes 1.

To generate the same output stream, the order of the taps is the counterpart (see above) of the order for the conventional LFSR, otherwise the stream will be in reverse. Note that the internal state of the LFSR is not necessarily the same. The Galois register shown has the same output stream as the Fibonacci register in the first section. A time offset exists between the streams, so a different startpoint will be needed to get the same output each cycle.

Below is a C code example for the 16-bit maximal-period Galois LFSR example in the figure:

  1. include

unsigned lfsr_galois(void)

The branch if (lsb) lfsr ^= 0xB400u;can also be written as lfsr ^= (-lsb) & 0xB400u; which may produce more efficient code on some compilers. In addition, the left-shifting variant may produce even better code, as the msb is the carry from the addition of lfsr to itself.

Galois LFSR parallel computation

State and resulting bits can also be combined and computed in parallel. The following function calculates the next 64 bits using 63-bit polynomial x⁶³ + x⁶² + 1:

  1. include

uint64_t prsg63(uint64_t lfsr)

Non-binary Galois LFSR

Binary Galois LFSRs like the ones shown above can be generalized to any q-ary alphabet (e.g., for binary, q = 2, and the alphabet is simply). In this case, the exclusive-or component is generalized to addition modulo-q (note that XOR is addition modulo 2), and the feedback bit (output bit) is multiplied (modulo-q) by a q-ary value, which is constant for each specific tap point. Note that this is also a generalization of the binary case, where the feedback is multiplied by either 0 (no feedback, i.e., no tap) or 1 (feedback is present). Given an appropriate tap configuration, such LFSRs can be used to generate Galois fields for arbitrary prime values of q.

Xorshift LFSRs

See main article: Xorshift. As shown by George Marsaglia[6] and further analysed by Richard P. Brent,[7] linear feedback shift registers can be implemented using XOR and Shift operations. This approach lends itself to fast execution in software because these operations typically map efficiently into modern processor instructions.

Below is a C code example for a 16-bit maximal-period Xorshift LFSR using the 7,9,13 triplet from John Metcalf:[8]

  1. include

unsigned lfsr_xorshift(void)

Matrix forms

Binary LFSRs of both Fibonacci and Galois configurations can be expressed as linear functions using matrices in

F2

(see GF(2)).[9] Using the companion matrix of the characteristic polynomial of the LFSR and denoting the seed as a column vector

(a0,a1,...,an-1)T

, the state of the register in Fibonacci configuration after

k

steps is given by

\begin{pmatrix}ak\ak+1\ak+2\\vdots\ak+n-1\end{pmatrix}= \begin{pmatrix}0&1&0&&0\ 0&0&1&\ddots&\vdots\\vdots&\vdots&\ddots&\ddots&0\ 0&0&&0&1\c0&c1&&&cn-1\end{pmatrix} \begin{pmatrix}ak-1\ak\ak+1\\vdots\ak+n-2\end{pmatrix}= \begin{pmatrix}0&1&0&&0\ 0&0&1&\ddots&\vdots\\vdots&\vdots&\ddots&\ddots&0\ 0&0&&0&1\c0&c1&&&cn-1\end{pmatrix}k \begin{pmatrix}a0\a1\a2\\vdots\an-1\end{pmatrix}

Matrix for the corresponding Galois form is :

\begin{pmatrix}c0&1&0&&0\c1&0&1&\ddots&\vdots\\vdots&\vdots&\ddots&\ddots&0\cn-2&0&&0&1\cn-1&0&&&0\end{pmatrix}

For a suitable initialisation,

a'i=\sum

ja
i-j

cn-j, 0\leqi<n

the top coefficient of the column vector :

\begin{pmatrix}c0&1&0&&0\c1&0&1&\ddots&\vdots\\vdots&\vdots&\ddots&\ddots&0\cn-2&0&&0&1\cn-1&0&&&0\end{pmatrix}k \begin{pmatrix}a'0\a'1\a'2\\vdots\a'n-1\end{pmatrix}

gives the term of the original sequence.

These forms generalize naturally to arbitrary fields.

Example polynomials for maximal LFSRs

The following table lists examples of maximal-length feedback polynomials (primitive polynomials) for shift-register lengths up to 24. The formalism for maximum-length LFSRs was developed by Solomon W. Golomb in his 1967 book.[10] The number of different primitive polynomials grows exponentially with shift-register length and can be calculated exactly using Euler's totient function[11] .

Bits (n)Feedback polynomialTapsTaps (hex)Period (

2n-1

)
2

x2+x+1

110x33
3

x3+x2+1

1100x67
4

x4+x3+1

11000xC15
5

x+x+1

101000x1431
6

x+x+1

1100000x3063
7

x+x+1

11000000x60127
8

x+x+x+x+1

101110000xB8255
9

x+x+1

1000100000x110511
10

x+x+1

10010000000x2401,023
11

x+x+1

101000000000x5002,047
12

x+x+x+x+1

1110000010000xE084,095
13

x+x+x+x+1

11100100000000x1C808,191
14

x+x+x+x+1

111000000000100x380216,383
15

x+x+1

1100000000000000x600032,767
16

x+x+x+x+1

11010000000010000xD00865,535
17

x+x+1

100100000000000000x12000131,071
18

x+x+1

1000000100000000000x20400262,143
19

x+x+x+x+1

11100100000000000000x72000524,287
20

x+x+1

100100000000000000000x900001,048,575
21

x+x+1

1010000000000000000000x1400002,097,151
22

x+x+1

11000000000000000000000x3000004,194,303
23

x+x+1

100001000000000000000000x4200008,388,607
24

x+x+x+x+1

1110000100000000000000000xE1000016,777,215

Xilinx published an extended list of tap counters up to 168 bit. Tables of maximum length polynomials are available from http://users.ece.cmu.edu/~koopman/lfsr/ and can be generated by the https://github.com/hayguen/mlpolygen project.

Output-stream properties

Applications

LFSRs can be implemented in hardware, and this makes them useful in applications that require very fast generation of a pseudo-random sequence, such as direct-sequence spread spectrum radio. LFSRs have also been used for generating an approximation of white noise in various programmable sound generators.

Uses as counters

The repeating sequence of states of an LFSR allows it to be used as a clock divider or as a counter when a non-binary sequence is acceptable, as is often the case where computer index or framing locations need to be machine-readable.[12] LFSR counters have simpler feedback logic than natural binary counters or Gray-code counters, and therefore can operate at higher clock rates. However, it is necessary to ensure that the LFSR never enters an all-zeros state, for example by presetting it at start-up to any other state in the sequence.The table of primitive polynomials shows how LFSRs can be arranged in Fibonacci or Galois form to give maximal periods. One can obtain any other period by adding to an LFSR that has a longer period some logic that shortens the sequence by skipping some states.

Uses in cryptography

LFSRs have long been used as pseudo-random number generators for use in stream ciphers, due to the ease of construction from simple electromechanical or electronic circuits, long periods, and very uniformly distributed output streams. However, an LFSR is a linear system, leading to fairly easy cryptanalysis. For example, given a stretch of known plaintext and corresponding ciphertext, an attacker can intercept and recover a stretch of LFSR output stream used in the system described, and from that stretch of the output stream can construct an LFSR of minimal size that simulates the intended receiver by using the Berlekamp-Massey algorithm. This LFSR can then be fed the intercepted stretch of output stream to recover the remaining plaintext.

Three general methods are employed to reduce this problem in LFSR-based stream ciphers:

Important LFSR-based stream ciphers include A5/1 and A5/2, used in GSM cell phones, E0, used in Bluetooth, and the shrinking generator. The A5/2 cipher has been broken and both A5/1 and E0 have serious weaknesses.[14]

The linear feedback shift register has a strong relationship to linear congruential generators.[15]

Uses in circuit testing

LFSRs are used in circuit testing for test-pattern generation (for exhaustive testing, pseudo-random testing or pseudo-exhaustive testing) and for signature analysis.

Test-pattern generation

Complete LFSR are commonly used as pattern generators for exhaustive testing, since they cover all possible inputs for an n-input circuit. Maximal-length LFSRs and weighted LFSRs are widely used as pseudo-random test-pattern generators for pseudo-random test applications.

Signature analysis

In built-in self-test (BIST) techniques, storing all the circuit outputs on chip is not possible, but the circuit output can be compressed to form a signature that will later be compared to the golden signature (of the good circuit) to detect faults. Since this compression is lossy, there is always a possibility that a faulty output also generates the same signature as the golden signature and the faults cannot be detected. This condition is called error masking or aliasing. BIST is accomplished with a multiple-input signature register (MISR or MSR), which is a type of LFSR. A standard LFSR has a single XOR or XNOR gate, where the input of the gate is connected to several "taps" and the output is connected to the input of the first flip-flop. A MISR has the same structure, but the input to every flip-flop is fed through an XOR/XNOR gate. For example, a 4-bit MISR has a 4-bit parallel output and a 4-bit parallel input. The input of the first flip-flop is XOR/XNORd with parallel input bit zero and the "taps". Every other flip-flop input is XOR/XNORd with the preceding flip-flop output and the corresponding parallel input bit. Consequently, the next state of the MISR depends on the last several states opposed to just the current state. Therefore, a MISR will always generate the same golden signature given that the input sequence is the same every time.Recent applications[16] are proposing set-reset flip-flops as "taps" of the LFSR. This allows the BIST system to optimise storage, since set-reset flip-flops can save the initial seed to generate the whole stream of bits from the LFSR. Nevertheless, this requires changes in the architecture of BIST, is an option for specific applications.

Uses in digital broadcasting and communications

Scrambling

See main article: Scrambler. To prevent short repeating sequences (e.g., runs of 0s or 1s) from forming spectral lines that may complicate symbol tracking at thereceiver or interfere with other transmissions, the data bit sequence is combined with the output of a linear-feedback register before modulation and transmission. This scrambling is removed at the receiver after demodulation. When the LFSR runs at the same bit rate as the transmitted symbol stream, this technique is referred to as scrambling. When the LFSR runs considerably faster than the symbol stream, the LFSR-generated bit sequence is called chipping code. The chipping code is combined with the data using exclusive or before transmitting using binary phase-shift keying or a similar modulation method. The resulting signal has a higher bandwidth than the data, and therefore this is a method of spread-spectrum communication. When used only for the spread-spectrum property, this technique is called direct-sequence spread spectrum; when used to distinguish several signals transmitted in the same channel at the same time and frequency, it is called code-division multiple access.

Neither scheme should be confused with encryption or encipherment; scrambling and spreading with LFSRs do not protect the information from eavesdropping. They are instead used to produce equivalent streams that possess convenient engineering properties to allow robust and efficient modulation and demodulation.

Digital broadcasting systems that use linear-feedback registers:

Other digital communications systems using LFSRs:

Other uses

LFSRs are also used in radio jamming systems to generate pseudo-random noise to raise the noise floor of a target communication system.

The German time signal DCF77, in addition to amplitude keying, employs phase-shift keying driven by a 9-stage LFSR to increase the accuracy of received time and the robustness of the data stream in the presence of noise.[18]

See also

Further reading

External links

Notes and References

  1. Web site: Cyclic Redundancy Check Computation: An Implementation Using the TMS320C54x. Geremia. Patrick. Texas Instruments. 6. October 16, 2016.
  2. http://www.xilinx.com/support/documentation/application_notes/xapp210.pdf Linear Feedback Shift Registers in Virtex Devices
  3. Book: Gentle, James E. . Random number generation and Monte Carlo methods . 2003 . Springer . 0-387-00178-6 . 2nd . New York . 38 . 51534945.
  4. Tausworthe . Robert C. . April 1965 . Random Numbers Generated by Linear Recurrence Modulo Two . Mathematics of Computation . 19 . 90 . 201–209. 10.1090/S0025-5718-1965-0184406-1 . 120804149 .
  5. Book: Press . William . Teukolsky . Saul . Vetterling . William . Flannery . Brian . Numerical Recipes: The Art of Scientific Computing, Third Edition . . 2007 . 386 . 978-0-521-88407-5.
  6. George . Marsaglia . George Marsaglia. Xorshift RNGs. Journal of Statistical Software. 8 . 14. July 2003. 10.18637/jss.v008.i14. free.
  7. Richard P. . Brent . Richard P. Brent. Note on Marsaglia's Xorshift Random Number Generators. Journal of Statistical Software. 11 . 5. August 2004. 10.18637/jss.v011.i05. free. 1885/34049. free.
  8. Web site: Metcalf . John . 16-Bit Xorshift Pseudorandom Numbers in Z80 Assembly . Retro Programming . 5 January 2022. 22 July 2017.
  9. Book: Klein, A.. Stream Ciphers. Linear Feedback Shift Registers. 2013. 17–18. Springer. London. 10.1007/978-1-4471-5079-4_2. 978-1-4471-5079-4.
  10. Book: Golomb . Solomon W. . Shift register sequences . 1967 . Aegean Park Press . Laguna Hills, Calif. . 978-0894120480.
  11. Web site: Weisstein. Eric W.. Primitive Polynomial. 2021-04-27. mathworld.wolfram.com. en.
  12. http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
  13. A. Poorghanad, A. Sadr, A. Kashanipour" Generating High Quality Pseudo Random Number Using Evolutionary Methods", IEEE Congress on Computational Intelligence and Security, vol. 9, pp. 331-335, May, 2008 http://www.computer.org/csdl/proceedings/cis/2008/3508/01/3508a331.pdf
  14. Book: Lu, Yi . Willi Meier . Serge Vaudenay . Advances in Cryptology – CRYPTO 2005 . The Conditional Correlation Attack: A Practical Attack on Bluetooth Encryption . Crypto 2005 . 2005 . Santa Barbara, California, USA . 3621 . 97–117 . 10.1007/11535218_7. Lecture Notes in Computer Science . 978-3-540-28114-6 . 10.1.1.323.9416 .
  15. RFC 4086section 6.1.3 "Traditional Pseudo-random Sequences"
  16. Martínez LH, Khursheed S, Reddy SM. LFSR generation for high test coverage and low hardware overhead. IET Computers & Digital Techniques. 2019 Aug 21.UoL repository
  17. Section 9.5 of the SATA Specification, revision 2.6
  18. Time dissemination via the LF transmitter DCF77 using a pseudo-random phase-shift keying of the carrier . P. . Hetzel . 16 March 1988 . 2nd European Frequency and Time Forum . Neuchâtel . 351–364 . 11 October 2011.