Front end of line explained

The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate.^[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.^[2]

Steps

For the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:^{[3] [4]}

1. Selecting the type of wafer to be used; Chemical-mechanical planarization (CMP) and cleaning of the wafer.
2. Shallow trench isolation (STI) (or LOCOS in early processes with feature size > 0.25 μm);
3. Well formation;
4. Gate module formation;
5. Source and drain module formation.

Finally, the surface is treated to prepare the contacts for the subsequent metallization. This concludes the FEOL process, that is, all devices have been built.

Following these steps, the devices must be connected electrically as per the nets to build the electrical circuit. This is done in the back end of line (BEOL). BEOL is thus the second portion of IC fabrication where the individual devices are connected.

See also

• Back end of line (BEOL)
• Integrated circuit

Further reading

• "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. . pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
• "Fundamentals of Layout Design for Electronic Circuits", by Lienig, Scheible, Springer,, 2020. Chapter 2: Technology Know-How: From Silicon to Devices, pages 78-82 (2.9.3 FEOL: Creating Devices)

Notes and References

1. Book: Handbook of Silicon Wafer Cleaning Technology . 2nd . Karen A. Reinhardt and Werner Kern . William Andrew . 2008 . 978-0-8155-1554-8 . 202 .
2. Web site: 2019-02-22 . FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation USJC：United Semiconductor Japan Co., Ltd. . 2022-09-27 . USJC：United Semiconductor Japan Co., Ltd. 三重県桑名市の300mm半導体ウェーハ工場を製造拠点にしたファウンドリ専業メーカーです。超低消費電力、不揮発メモリなど先進テクノロジーを世界中のお客様に提供しています。 . ja.
3. Web site: Ramsundar . Bharath . A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics . 2022-09-27 . deepforest.substack.com . en.
4. Book: J. Lienig, J. Scheible. Fundamentals of Layout Design for Electronic Circuits. 78–82. Chap. 2.9.3: FEOL: Creating Devices. Springer. 2020. 10.1007/978-3-030-39284-0. 978-3-030-39284-0. 215840278.