| eSi-RISC | |
| Designer: | eSi-RISC |
| Bits: | 16-bit/32-bit |
| Introduced: | 2009 |
| Design: | RISC |
| Type: | Load–store |
| Encoding: | Intermixed 16 and 32-bit |
| Branching: | Compare and branch and condition code |
| Endianness: | Big or little |
| Extensions: | User-defined instructions |
| Registers: | 8/16/32 General Purpose, 8/16/32 Vector |
eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264.[1] The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.[2]
The main features of the eSi-RISC architecture are:[3]
While there are many different 16 or 32-bit Soft microprocessor IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.
Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.
eSi-RISC includes support for Multiprocessing. Implementations have included up to seven eSi-3250's on a single chip.[5]
The eSi-RISC toolchain is based on combination of a port of the GNU toolchain and the Eclipse IDE.[6] This includes:
The C library is Newlib and the C++ library is Libstdc++. Ported RTOSes include MicroC/OS-II, FreeRTOS, ERIKA Enterprise[7] and Phoenix-RTOS[8]