| Alpha | |
| Designer: | Digital Equipment Corporation |
| Bits: | 64-bit |
| Design: | RISC |
| Type: | Load–store |
| Encoding: | Fixed |
| Endianness: | Bi |
| Extensions: | Byte/Word Extension (BWX), Square-root and Floating-point Convert Extension (FIX), Count Extension (CIX), Motion Video Instructions (MVI) |
| Open: | Yes |
| Gpr: | 31 plus always-zero R31 |
| Fpr: | 31 plus always-0.0 F31 |
Alpha (original name Alpha AXP) is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.
Alpha is implemented in a series of microprocessors originally developed and fabricated by DEC. These microprocessors are most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards.
Operating systems that support Alpha included OpenVMS (formerly named OpenVMS AXP), Tru64 UNIX (formerly named DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4.0; and prerelease Windows 2000 RC2),[1] Linux (Debian, SUSE,[2] Gentoo and Red Hat), BSD UNIX (NetBSD, OpenBSD and FreeBSD up to 6.x), Plan 9 from Bell Labs, and the L4Ka::Pistachio kernel. A port of Ultrix to Alpha was carried out during the initial development of the Alpha architecture, but was never released as a product.[3]
The Alpha architecture was sold, along with most parts of DEC, to Compaq in 1998.[4] Compaq, already an Intel x86 customer, announced that they would phase out Alpha in favor of the forthcoming Hewlett-Packard/Intel Itanium architecture, and sold all Alpha intellectual property to Intel, in 2001,[5] effectively killing the product. Hewlett-Packard purchased Compaq in 2002, continuing development of the existing product line until 2004, and selling Alpha-based systems, largely to the existing customer base, until April 2007.[6]
See main article: DEC PRISM. Alpha emerged from an earlier RISC project named Parallel Reduced Instruction Set Machine (PRISM), itself the product of several earlier projects. PRISM was intended to be a flexible design, supporting Unix-like applications, and Digital's existing VAX/VMS software, after minor conversion. A new operating system named MICA would support both ULTRIX and VAX/VMS interfaces on a common kernel, allowing software for both platforms to be easily ported to the PRISM architecture.[7]
Started in 1985, the PRISM design was continually changed during its development in response to changes in the computer market, leading to lengthy delays in its introduction. It was not until the summer of 1987 that it was decided that it would be a 64-bit design, among the earliest such designs in a microprocessor format. In October 1987, Sun Microsystems introduced the Sun-4, their first workstation using their new SPARC processor. The Sun-4 runs about three to four times as fast as their latest Sun-3 designs using the Motorola 68020, and any Unix offering from DEC. The plans changed again; PRISM was realigned once again as a 32-bit part and aimed directly at the Unix market. This further delayed the design.[8]
Having watched the PRISM delivery date continue to slip, and facing the possibility of more delays, a team in the Palo Alto office decided to design their own workstation using another RISC processor. After due diligence, they selected the MIPS R2000 and built a working workstation running Ultrix in a period of 90 days.[9] This sparked off an acrimonious debate within the company, which came to a head in a July 1988 management meeting. PRISM appeared to be faster than the R2000, but the R2000 machines could be in the market by January 1989, a year earlier than PRISM. When this proposal was accepted, one of the two original roles for PRISM disappeared. The decision to make a VMS PRISM had already ended by this point, so there was no remaining role. PRISM was cancelled at the meeting.[10]
As the meeting broke up, Bob Supnik was approached by Ken Olsen, who stated that the RISC chips appeared to be a future threat to their VAX line. He asked Supnik to consider what might be done with VAX to keep it competitive with future RISC systems.[8]
This led to the formation of the "RISCy VAX" team. They initially considered three concepts. One was a cut-down version of the VAX instruction set architecture (ISA) that would run on a RISC-like system and leave more complex VAX instructions to system subroutines. Another concept was a pure RISC system that would translate existing VAX code into its own ISA on-the-fly and store it in a CPU cache. Finally, there was still the possibility of a much faster CISC processor running the complete VAX ISA. Unfortunately, all of these approaches introduced overhead and would not be competitive with a pure-RISC machine running native RISC code.[11]
The group then considered hybrid systems that combined one of their existing VAX one-chip solution and a RISC chip as a coprocessor used for high-performance needs. These studies suggested that the system would inevitably be hamstrung by the lower-performance part and would offer no compelling advantage. It was at this point that Nancy Kronenberg pointed out that people ran VMS, not VAX, and that VMS only had a few hardware dependencies based on its modelling of interrupts and memory paging. There appeared to be no compelling reason why VMS could not be ported to a RISC chip as long as these small bits of the model were preserved. Further work on this concept suggested this was a workable approach.[11]
Supnik took the resulting report to the Strategy Task Force in February 1989. Two questions were raised: could the resulting RISC design also be a performance leader in the Unix market, and should the machine be an open standard? And with that, the decision was made to adopt the PRISM architecture with the appropriate modifications. This became the "EVAX" concept, a follow-on to the successful CMOS CVAX implementation. When management accepted the findings, they decided to give the project a more neutral name, removing "VAX", eventually settling on Alpha.[12] The name was inspired by the use of "Omega" as the codename of an NVAX-based VAX 4000 model; "Alpha" was intended to signify the beginning of a new line (with reference to Alpha and Omega).[13] Soon after, work began on a port of VMS to the new architecture.[14]
The new design uses most of the basic PRISM concepts, but was re-tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all. The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek.[15] The PRISM's Epicode was developed into the Alpha's PALcode, providing an abstracted interface to platform- and processor implementation-specific features.
The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, is not so much the architecture but rather its implementation.[16] At that time (as it is now), the microchip industry was dominated by automated design and layout tools. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the complex VAX architecture. The Alpha chips show that manual circuit design applied to a simpler, cleaner architecture allows for much higher operating frequencies than those that are possible with the more automated design systems. These chips caused a renaissance of custom circuit design within the microprocessor design community.
Originally, the Alpha processors were designated the DECchip 21x64 series,[17] with "DECchip" replaced in the mid-1990s with "Alpha". The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits.[17] The Alpha was designed as 64-bit from the start and there is no 32-bit version. The middle digit corresponds to the generation of the Alpha architecture. Internally, Alpha processors were also identified by EV numbers, EV officially standing for "Extended VAX" but having an alternative humorous meaning of "Electric Vlasic", giving homage to the Electric Pickle experiment at Western Research Lab.[18]
In May 1997, DEC sued Intel for allegedly infringing on its Alpha patents in designing the original Pentium, Pentium Pro, and Pentium II chips.[19] As part of a settlement, much of DEC's chip design and fabrication business was sold to Intel. This included DEC's StrongARM implementation of the ARM computer architecture, which Intel marketed as the XScale processors commonly used in Pocket PCs. The core of Digital Semiconductor, the Alpha microprocessor group, remained with DEC, while the associated office buildings went to Intel as part of the Hudson fab.[20]
The first few generations of the Alpha chips were some of the most innovative of their time.
A persistent report attributed to DEC insiders suggests the choice of the AXP tag for the processor was made by DEC's legal department, which was still smarting from the VAX trademark fiasco.[25] After a lengthy search the tag "AXP" was found to be entirely unencumbered. Within the computer industry, a joke got started that the acronym AXP meant "Almost eXactly PRISM".
The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years. To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have:
The Alpha does not have condition codes for integer instructions[28] to remove a potential bottleneck at the condition status register. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 least significant bits to the destination register. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.
| + DEC Alpha registers | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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The architecture defines a set of 32 integer registers and a set of 32 floating-point registers in addition to a program counter, two lock registers and a floating-point control register (FPCR). It also defines registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcode are defined.
The integer registers are denoted by R0 to R31 and floating-point registers are denoted by F0 to F31. The R31 and F31 registers are hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better, as it enables two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating-point registers. A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports. The number of registers per register file was also considered, with 32 and 64 being contenders. Digital concluded that 32 registers was more suitable as it required less die space, which improves clock frequencies. This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty-two registers could support at least eight-way instruction issue.
The program counter is a 64-bit register which contains a longword-aligned virtual byte address, that is, the low two bits of the program counter are always zero. The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support. The floating-point control register (FPCR) is a 64-bit register defined by the architecture intended for use by Alpha implementations with IEEE 754-compliant floating-point hardware.
In the Alpha architecture, a byte is defined as an 8-bit datum (octet), a word as a 16-bit datum, a longword as a 32-bit datum, a quadword as a 64-bit datum, and an octaword as a 128-bit datum.
The Alpha architecture originally defined six data types:
To maintain a level of compatibility with the VAX, the 32-bit architecture that preceded the Alpha, two other floating-point data types are included:
VAX H-floating point (quad precision, 128-bit) was not supported,[29] but another 128-bit floating-point option, X-floating point, is available on Alpha, but not VAX.[30]
H and X have been described as similar, but not identical. Software emulation for H-floating is available from DEC, as is a source-code level converter named DECmigrate.
The Alpha has a 64-bit linear virtual address space with no memory segmentation. Implementations can implement a smaller virtual address space with a minimum size of 43 bits. Although the unused bits were not implemented in hardware such as TLBs, the architecture required implementations to check whether they are zero to ensure software compatibility with implementations with a larger (or full) virtual address space.
The Alpha ISA has a fixed instruction length of 32 bits. It has six instruction formats.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Type |
| Opcode | Ra | Rb | Unused | 0 | Function | Rc | Integer operate | |||||||||||||||||||||||||
| Opcode | Ra | Literal | 1 | Function | Rc | Integer operate, literal | ||||||||||||||||||||||||||
| Opcode | Ra | Rb | Function | Rc | Floating-point operate | |||||||||||||||||||||||||||
| Opcode | Ra | Rb | Displacement | Memory format | ||||||||||||||||||||||||||||
| Opcode | Ra | Displacement | Branch format | |||||||||||||||||||||||||||||
| Opcode | Function | CALL_PAL format | ||||||||||||||||||||||||||||||
The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format. A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to. The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers.
The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement of the 5-bit Rb field and the 3 bits of unused space with an 8-bit literal field which is zero-extended to a 64-bit operand.
The floating-point operate format is used by floating-point instructions. It is similar to the integer operate format, but has an 11-bit function field made possible by using the literal and unused bits which are reserved in integer operate format.
The memory format is used mostly by load and store instructions. It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field.
Branch instructions have a 6-bit opcode field, a 5-bit Ra field and a 21-bit displacement field. The Ra field specifies a register to be tested by a conditional branch instruction, and if the condition is met, the program counter is updated by adding the contents of the displacement field with the program counter. The displacement field contains a signed integer and if the value of the integer is positive, if the branch is taken then the program counter is incremented. If the value of the integer is negative, then program counter is decremented if the branch is taken. The range of a branch thus is ±1 Mi instructions, or ±4 MiB. The Alpha Architecture was designed with a large range as part of the architecture's forward-looking goal.
The CALL_PAL format is used by the CALL_PAL instruction, which is used to call PALcode subroutines. The format retains the opcode field but replaces the others with a 26-bit function field, which contains an integer specifying a PAL subroutine.
The control instructions consist of conditional and unconditional branches, and jumps. The conditional and unconditional branch instructions use the branch instruction format, while the jump instructions use the memory instruction format.
Conditional branches test whether the least significant bit of a register is set or clear, or compare a register as a signed quadword to zero, and branch if the specified condition is true. The conditions available for comparing a register to zero are equality, inequality, less than, less than or equal to, greater than or equal to, and greater than. The new address is computed by longword aligning and sign extending the 21-bit displacement and adding it to the address of the instruction following the conditional branch.
Unconditional branches update the program counter with a new address computed in the same way as conditional branches. They also save the address of the instruction following the unconditional branch to a register. There are two such instructions, and they differ only in the hints provided for the branch prediction hardware.
There are four jump instructions. These all perform the same operation, saving the address of the instruction following the jump, and providing the program counter with a new address from a register. They differ in the hints provided to the branch prediction hardware. The unused displacement field is used for this purpose.
The integer arithmetic instructions perform addition, multiplication, and subtraction on longwords and quadwords; and comparison on quadwords. There is no instruction(s) for division as the architects considered the implementation of division in hardware to be adverse to simplicity. In addition to the standard add and subtract instructions, there are scaled versions. These versions shift the second operand to the left by two or three bits before adding or subtracting. The Multiply Longword and Multiply Quadword instructions write the least significant 32 or 64 bits of a 64- or 128-bit result to the destination register, respectively. Since it is useful to obtain the most significant half, the Unsigned Multiply Quadword High (UMULH) instruction is provided. UMULH is used for implementing multi-precision arithmetic and division algorithms. The concept of a separate instruction for multiplication that returns the most significant half of a result was taken from PRISM.
The instructions that operate on longwords ignore the most significant half of the register and the 32-bit result is sign-extended before it is written to the destination register. By default, the add, multiply, and subtract instructions, with the exception of UMULH and scaled versions of add and subtract, do not trap on overflow. When such functionality is required, versions of these instructions that perform overflow detection and trap on overflow are provided.
The compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' if not. The conditions are equality, inequality, less than or equal to, and less than. With the exception of the instructions that specify the former two conditions, there are versions that perform signed and unsigned compares.
The integer arithmetic instructions use the integer operate instruction formats.
The logical instructions consist of those for performing bitwise logical operations and conditional moves on the integer registers. The bitwise logical instructions perform AND, NAND, NOR, OR, XNOR, and XOR between two registers or a register and literal. The conditional move instructions test a register as a signed quadword to zero and move if the specified condition is true. The specified conditions are equality, inequality, less than or equal to, less than, greater than or equal to, and greater than. The shift instructions perform arithmetic right shift, and logical left and right shifts. The shift amount is given by a register or literal. Logical and shift instructions use the integer operate instruction formats.
Later Alphas include byte-word extensions, a set of instructions to manipulate 8-bit and 16-bit data types. These instructions were first introduced in the 21164A (EV56) microprocessor and are present in all subsequent implementations. These instructions perform operations that formerly required multiple instructions to implement, which improves code density and the performance of certain applications. BWX also makes the emulation of x86 machine code and the writing of device drivers easier.[31]
| Mnemonic | Instruction |
|---|---|
LDBU | Load Zero-Extended Byte from Memory to Register |
LDWU | Load Zero-Extended Word from Memory to Register |
SEXTB | Sign Extend Byte |
SEXTW | Sign Extend Word |
STB | Store Byte from Register to Memory |
STW | Store Word from Register to Memory |
Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for single instruction, multiple data (SIMD) operations.[32] Alpha implementations that implement MVI, in chronological order, are the Alpha 21164PC (PCA56 and PCA57), Alpha 21264 (EV6) and Alpha 21364 (EV7). Unlike most other SIMD instruction sets of the same period, such as MIPS' MDMX or SPARC's Visual Instruction Set, but like PA-RISC's Multimedia Acceleration eXtensions (MAX-1, MAX-2), MVI was a simple instruction set composed of a few instructions that operate on integer data types stored in existing integer registers.
MVI's simplicity is due to two reasons. Firstly, Digital had determined that the Alpha 21164 was already capable of performing DVD decoding through software, therefore not requiring hardware provisions for the purpose, but was inefficient in MPEG-2 encoding. The second reason is the requirement to retain the fast cycle times of implementations. Adding many instructions would have complicated and enlarged the instruction decode logic, reducing an implementation's clock frequency.
MVI consists of 13 instructions:
| Mnemonic | Instruction |
|---|---|
MAXSB8 | Vector Signed Byte Maximum |
MAXSW4 | Vector Signed Word Maximum |
MAXUB8 | Vector Unsigned Byte Maximum |
MAXUW4 | Vector Unsigned Word Maximum |
MINSB8 | Vector Signed Byte Minimum |
MINSW4 | Vector Signed Word Minimum |
MINUB8 | Vector Unsigned Byte Minimum |
MINUW4 | Vector Unsigned Word Minimum |
PERR | Pixel Error |
PKLB | Pack Longwords to Bytes |
PKWB | Pack Words to Bytes |
UNPKBL | Unpack Bytes to Longwords |
UNPKBW | Unpack Bytes to Words |
Floating-point extensions (FIX) are an extension to the Alpha Architecture. It introduces nine instructions for floating-point square-root and for transferring data to and from the integer registers and floating-point registers. The Alpha 21264 (EV6) is the first microprocessor to implement these instructions.
| Mnemonic | Instruction |
|---|---|
FTOIS | Floating-point to Integer Register Move, S_floating |
FTOIT | Floating-point to Integer Register Move, T_floating |
ITOFF | Integer to Floating-point Register Move, F_floating |
ITOFS | Integer to Floating-point Register Move, S_floating |
ITOFT | Integer to Floating-point Register Move, T_floating |
SQRTF | Square root F_floating |
SQRTG | Square root G_floating |
SQRTS | Square root S_floating |
SQRTT | Square root T_floating |
Count Extensions (CIX) is an extension to the architecture which introduces three instructions for counting bits. These instructions are categorized as integer arithmetic instructions. They were first implemented on the Alpha 21264A (EV67).
| Mnemonic | Instruction |
|---|---|
CTLZ | Count Leading Zero |
CTPOP | Count Population |
CTTZ | Count Trailing Zero |
At the time of its announcement, Alpha was heralded as an architecture for the next 25 years. While this was not to be, Alpha has nevertheless had a reasonably long life. The first version, the Alpha 21064 (otherwise named the EV4) was introduced in November 1992 running at up to 192 MHz; a slight shrink of the die (the EV4S, shrunk from 0.75 μm to 0.675 μm) ran at 200 MHz a few months later. The 64-bit processor was a superpipelined and superscalar design, like other RISC designs, but nevertheless outperformed them all and DEC touted it as the world's fastest processor. Careful attention to circuit design, a hallmark of the Hudson design team, like a huge centralized clock circuitry, allowed them to run the CPU at higher speeds, even though the microarchitecture was fairly similar to other RISC chips. In comparison, the less expensive Intel Pentium ran at 66 MHz when it was launched the following spring.
The Alpha 21164 or EV5 became available in 1995 at processor frequencies of up to 333 MHz. In July 1996 the line was speed bumped to 500 MHz, in March 1998 to 666 MHz. Also in 1998 the Alpha 21264 (EV6) was released at 450 MHz, eventually reaching (in 2001 with the 21264C/EV68CB) 1.25 GHz. In 2003, the Alpha 21364 or EV7 Marvel was launched, essentially an EV68 core with four 1.6 GB/s inter-processor communication links for improved multiprocessor system performance, running at 1 or 1.15 GHz.
In 1996, the production of Alpha chips was licensed to Samsung Electronics Company. Following the purchase of Digital by Compaq the majority of the Alpha products were placed with API NetWorks, Inc. (formerly Alpha Processor Inc.), a private company funded by Samsung and Compaq. In October 2001, Microway became the exclusive sales and service provider of API NetWorks' Alpha-based product line.
On June 25, 2001, Compaq announced that Alpha would be phased out by 2004 in favor of Intel's Itanium, canceled the planned EV8 chip, and sold all Alpha intellectual property to Intel.[5] Hewlett-Packard merged with Compaq in 2002; HP announced that development of the Alpha series would continue for a few more years, including the release of a 1.3 GHz EV7 variant named the EV7z. This would be the final iteration of Alpha, the 0.13 μm EV79 also being canceled.
Alpha is also implemented in the Piranha, a research prototype developed by Compaq's Corporate Research and Nonstop Hardware Development groups at the Western Research Laboratory and Systems Research Center. Piranha is a multicore design for transaction processing workloads that contains eight simple cores. It was described at the 27th Annual International Symposium on Computer Architecture in June 2000.[33]
Early revisions of the Sunway architecture are claimed to be based on Alpha, however since the SW26010, Sunway uses a new instruction set architecture unrelated to Alpha.[34] [35]
| Model | Model number | Year | Frequency [MHz] | Process [μm] | Transistors [millions] | Die size [mm<sup>2</sup>] | IO pins | Power [W] | Voltage | Dcache [KB][36] | Icache [KB] | Scache | Bcache | ISA | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EV4 | 21064 | 1992 | 100 - 200 | 0.75 | 1.68 | 234 | 290 | 30 | 3.3 | 8 | 8 | – | 128 KB - 16 MB | ||
| EV4S | 21064 | 1993 | 100 - 200 | 0.675 | 1.68 | 186 | 290 | 27 | 3.3 | 8 | 8 | – | 128 KB - 16 MB | ||
| EV45 | 21064A | 1994 | 200 - 300 | 0.5 | 2.85 | 164 | 33 | 3.3 | 16 | 16 | – | 256 KB - 16 MB | |||
| LCA4 | 21066 | 1993 | 100 - 166 | 0.675 | 1.75 | 209 | 21 | 3.3 | 8 | 8 | – | ||||
| LCA4 | 21068 | 1994 | 66 | 0.675 | 1.75 | 209 | 9 | 3.3 | 8 | 8 | – | ||||
| LCA45 | 21066A | 1994 | 100 - 266 | 0.5 | 1.8 | 161 | 23 | 3.3 | 8 | 8 | – | ||||
| LCA45 | 21068A | 1994 | 100 | 0.5 | 1.8 | 161 | 3.3 | 8 | 8 | – | |||||
| EV5 | 21164 | 1995 | 266 - 500 | 0.5 | 9.3 | 299 | 296 | 56 | 3.3/2.5 | 8 | 8 | 96 KB | Up to 64 MB | R | |
| EV56 | 21164A | 1996 | 366 - 666 | 0.35 | 9.66 | 209 | 31 - 55 | 3.3/2.5 | 8 | 8 | 96 KB | Up to 64 MB | R,B | ||
| PCA56 | 21164PC | 1997 | 400 - 533 | 0.35 | 3.5 | 141 | 264 | 26 - 35 | 3.3/2.5 | 8 | 16 | – | 512 KB - 4 MB | R,B,M | |
| PCA57 | 21164PC | 600 - 666 | 0.28 | 5.7 | 101 | 283 | 18 - 23 | 2.5/2.0 | 16 | 32[37] | – | 512 KB - 4 MB | R,B,M | ||
| EV6 | 21264 | 1998 | 450 - 600 | 0.35 | 15.2 | 314 | 389 | 73 | 2.0 | 64 | 64 | – | 2 - 8 MB | R,B,M,F | |
| EV67 | 21264A | 1999 | 600 - 750 | 0.25 | 15.2 | 210 | 389 | 2.0 | 64 | 64 | – | 2 - 8 MB | R,B,M,F,C | ||
| EV68AL | 21264B | 2001 | 800 - 833 | 0.18 | 15.2 | 125 | 1.7 | 64 | 64 | – | 2 - 8 MB | R,B,M,F,C,T | |||
| EV68CB | 21264C | 2001 | 1000 - 1250 | 0.18 | 15.2 | 125 | 65 - 75 | 1.65 | 64 | 64 | – | 2 - 8 MB | R,B,M,F,C,T | ||
| EV68CX | 21264D | 1.65 | 64 | 64 | – | 2 - 8 MB | R,B,M,F,C,T | ||||||||
| EV7 | 21364 | 2003 | 1000 - 1150 | 0.18 | 130 | 397 | 125 | 1.5 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T | ||
| EV7z | 21364 | 2004 | 1300 | 0.18 | 130 | 397 | 125 | 1.5 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T | ||
| Cancelled | |||||||||||||||
| EV78/EV79 | 21364A | Slated for 2004 | 1700 | 0.13 | 152 | 300 | 120 | 1.2 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T | ||
| EV8 | 21464 | Slated for 2003 | 1200 - 2000 | 0.125 | 250 | 420 | 1800 | ?? | 1.2 | 64 | 64 | 3 MB | – | R,B,M,F,C,T | |
To illustrate the comparative performance of Alpha-based systems, some Standard Performance Evaluation Corporation (SPEC) performance numbers (SPECint95, SPECfp95) are listed below. Note that the SPEC results claim to report the measured performance of a whole computer system (CPU, bus, memory, compiler optimizer), not just the CPU. Also note that the benchmark and scale changed from 1992 to 1995. However, the figures give a rough impression of the performance of the Alpha architecture (64-bit), compared with the contemporary HP (64-bit) and Intel-based offerings (32-bit). Perhaps the most obvious trend is that while Intel could always get reasonably close to Alpha in integer performance, in floating-point performance the difference was considerable. On the other side, HP (PA-RISC) is also reasonably close to Alpha, but these CPUs are running at significantly lower clock rates (MHz). The tables lack two important values: the power consumption and the price of a CPU.
| System | CPU | MHz | integer | floating point |
|---|---|---|---|---|
| +SPEC benchmark 1995 performance comparison (using SPECint95 and SPECfp95 results http://www.spec.org/cpu95/results/) | ||||
| AlphaServer 8400 5/350 | 21164 (EV5) | 350 | 10.1 | 14.2 |
| Intel Alder System (200 MHz, 256 KB L2) | Pentium Pro | 200 | 8.9 | 6.75 |
| HP 9000 C160 | PA-8000 | 160 | 10.4 | 16.3 |
| System | CPU | MHz | integer | floating point |
|---|---|---|---|---|
| +2000 performance comparison (using SPECint95 and SPECfp95 results) | ||||
| AlphaServer ES40 6/833 | 21264 (EV6) | 833 | 50.0 | 100.0 |
| Intel VC820 motherboard | Pentium III | 1000 | 46.8 | 31.9 |
| HP 9000 C3600 | PA-8600 | 552 | 42.1 | 64.0 |
The first generation of DEC Alpha-based systems comprise the DEC 3000 AXP series workstations and low-end servers, DEC 4000 AXP series mid-range servers, and DEC 7000 AXP and 10000 AXP series high-end servers. The DEC 3000 AXP systems use the same TURBOchannel bus as the prior MIPS-based DECstation models, whereas the 4000 is based on Futurebus+ and the 7000/10000 share an architecture with corresponding VAX models.
DEC also produced a personal computer (PC) configuration Alpha workstation with an Extended Industry Standard Architecture (EISA) bus, the DECpc AXP 150 (codename Jensen, also named the DEC 2000 AXP). This is the first Alpha system to support Windows NT. DEC later produced Alpha versions of their Celebris XL and Digital Personal Workstation PC lines, with 21164 processors.
Digital also produced single-board computers based on the VMEbus for embedded and industrial use. The first generation includes the 21068-based AXPvme 64 and AXPvme 64LC, and the 21066-based AXPvme 160. These were introduced on March 1, 1994. Later models such as the AXPvme 100, AXPvme 166 and AXPvme 230 are based on the 21066A processor, while the Alpha VME 4/224 and Alpha VME 4/288 are based on the 21064A processor. The last models, the Alpha VME 5/352 and Alpha VME 5/480, are based on the 21164 processor.
The 21066 chip is used in the DEC Multia VX40/41/42 compact workstation and the ALPHAbook 1 laptop from Tadpole Technology.
In 1994, DEC launched a new range of AlphaStation and AlphaServer systems. These use 21064 or 21164 processors and introduced the PCI bus, VGA-compatible frame buffers and PS/2-style keyboards and mice. The AlphaServer 8000 series supersedes the DEC 7000/10000 AXP and also employs XMI and FutureBus+ buses.
The AlphaStation XP1000 is the first workstation based on the 21264 processor. Later AlphaServer/Station models based on the 21264 are categorised into DS (departmental server), ES (enterprise server) or GS (global server) families.
The final 21364 chip is used in the AlphaServer ES47, ES80 and GS1280 models and the AlphaStation ES47.
A number of OEM motherboards were produced by DEC, such as the 21066 and 21068-based AXPpci 33 "NoName", which was part of a major push into the OEM market by the company,[39] the 21164-based AlphaPC 164 and AlphaPC 164LX, the 21164PC-based AlphaPC 164SX and AlphaPC 164RX and the 21264-based AlphaPC 264DP. Several third parties such as Samsung and API also produced OEM motherboards such as the API UP1000 and UP2000.
To assist third parties in developing hardware and software for the platform, DEC produced Evaluation Boards, such as the EB64+ and EB164 for the Alpha 21064A and 21164 microprocessors respectively.
The 21164 and 21264 processors were used by NetApp in various network-attached storage systems, while the 21064 and 21164 processors were used by Cray in their T3D and T3E massively parallel supercomputers.
The fastest supercomputer based on Alpha processors was the ASCI Q at Los Alamos National Laboratory. The machine was built as an HP AlphaServer SC45/GS Cluster. It had 4096 Alpha (21264 EV-68, 1.25 GHz) CPUs, and reached an Rmax of 7.727 TFLOPS.[40]