| Cooper Lake | |
| Soldby: | Intel |
| Designfirm: | Intel |
| Manuf1: | Intel |
| Code: | 80706 |
| Clock: | 4.3 |
| Qpi-Slow-Unit: | 10.4 |
| L1cache: | 64 KB per core(32 instructions + 32 data) |
| L2cache: | 1 MB per core |
| L3cache: | Up to 38.5 MB (1.375 MB/core) |
| Application: | 4S and 8S servers |
| Size-From: | 14 nm (Tri-Gate) transistors |
| Microarch: | Skylake |
| Arch: | x86-64 |
| Instructions: | MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, bfloat16 |
| Extensions: | AES-NI, CLMUL, RDRAND, TXT, FSGSBASE, MOVBE, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, MPX, TSX, VT-x, VT-d |
| Numcores: | 16-28 |
| Sock1: | LGA 4189 |
| Pcode1: | CPL |
| Model1: | Cooper Lake-SP |
| Brand1: | Xeon |
| Predecessor: | Cascade Lake |
| Successor: | Same generation
Next generation |
| Support Status: | Supported |
Cooper Lake is Intel's codename for the third-generation of their Xeon Scalable processors, developed as the successor to Cascade Lake-SP. Cooper Lake processors are targeted at the 4S and 8S segments of the server market; Ice Lake-SP serves the 1S and 2S segment.[1] [2] [3]
Cooper Lake was launched on June 18, 2020 and features up to 28 cores.[4] Aside from a few microarchitectural changes, Cooper Lake's microarchitecture is mostly identical to Skylake.[5] Cooper Lake features faster memory support (DDR4-3200 over DDR4-2933), support for second-generation Optane memory, and double the UPI links over Cascade Lake. Cooper Lake is the first x86 CPU to support the new bfloat16 instruction set as a part of Intel's Deep Learning Boost (DPL).
bfloat16 instruction