Control register explained

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

History

The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags.[1] When IBM developed a paging version of the System/360, they added 16 control registers to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard part of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS, S/370-XA, S/370-ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

Control registers in IBM 360/67

On the 360/67, CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode, and CR 8-14 contain the switch settings on the 2167 Configuration Unit.

M67 CR0

Control Register 0 contains the address of the segment table for dynamic address translation.

M67 CR2

Control register 2 is the Relocation exception address register.

M67 CR4

CR4 is the extended mask register for channels 0-31. Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR5

CR5 is reserved for the extended mask register for channels 32–63. Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR6

CR6 contains two mode flags plus extensions to the PSW mask bits.

CR6 Flags and Masks! Field !! Bit !! Description
00Machine Check Mask Extension for Channel Controller o
11Machine Check Mask Extension for Channel Controller 1
2-3Reserved for channel controllers 2-3
4-7Unassigned
88Extended Control Mode
99Configuration Control Bit
10-23Unassigned
24-31External interrupt masking
24 Timer
25Interrupt Key
26 Malfunction Alert - CPU 1 (Ext. Sig. 2)
27 Malfunction Alert - CPU 2 (Ext. Sig. 3)
28 Reserved (Ext. Sig. 4)
29 Reserved (Ext. Sig. 5)
30 External Interrupt - CPU 1, 2 (Ext. Sig. 6)
31 Reserved (Ext. Sig. 7)

M67 CR8

Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units (CPUs) and channel controllers (CCs).

Processor Storage unit 1-4 assignment! Bit !! Description
0Processor Storage Unit 1 to CPU 1
1Processor Storage Unit 1 to CPU 2
2-3Reserved for CPU 3-4
4Processor Storage Unit 1 to CC 0
5Processor Storage Unit 1 to CC 1
6-7Reserved for CC 3-4
8Processor Storage Unit 2 to CPU 1
9Processor Storage Unit 2 to CPU 2
10-11Reserved for CPU 3-4
12Processor Storage Unit 2 to CC 0
13Processor Storage Unit 2 to CC 1
14-15Reserved for CC 3-4
16Processor Storage Unit 3 to CPU 1
17Processor Storage Unit 3 to CPU 2
18-19Reserved for CPU 3-4
20Processor Storage Unit 3 to CC 0
21Processor Storage Unit 3 to CC 1
22-23Reserved for CC 3-4
24Processor Storage Unit 4 to CPU 1
25Processor Storage Unit 4 to CPU 2
26-27Reserved for CPU 3-4
28Processor Storage Unit 4 to CC 0
29Processor Storage Unit 4 to CC 1
30-31Reserved for CC 3-4

M67 CR9

Control Register 9 contains the assignments of Processor Storage units 5–8 to central processing units (CPUs) and channel controllers (CCs).

Processor Storage unit 1-4 assignment! Bit !! Description
0Processor Storage Unit 5 to CPU 1
1Processor Storage Unit 5 to CPU 2
2-3Reserved for CPU 3-4
4Processor Storage Unit 5 to CC 0
5Processor Storage Unit 5 to CC 1
6-7Reserved for CC 3-4
8Processor Storage Unit 6 to CPU 66
9Processor Storage Unit 6 to CPU 2
10-11Reserved for CPU 3-4
12Processor Storage Unit 6 to CC 0
13Processor Storage Unit 6 to CC 1
14-15Reserved for CC 3-4
16Processor Storage Unit 7 to CPU 1
17Processor Storage Unit 7 to CPU 2
18-19Reserved for CPU 3-4
20Processor Storage Unit 7 to CC 0
21Processor Storage Unit 7 to CC 1
22-23Reserved for CC 3-4
24Processor Storage Unit 8 to CPU 1
25Processor Storage Unit 8 to CPU 2
26-27Reserved for CPU 3-4
28Processor Storage Unit 8 to CC 0
29Processor Storage Unit 8 to CC 1
30-31Reserved for CC 3-4

M67 CR10

Control Register 10 contains the Processor storage address assignment codes.

Processor storage address bits 11-14 assignment codes! Bit !! Starting Address Code for
0-3Processor Storage Unit 1
4-7Processor Storage Unit 2
8-11Processor Storage Unit 3
12-15Processor Storage Unit 4
16-19Processor Storage Unit 5
20-23Processor Storage Unit 6
24-27Processor Storage Unit 7
28-31Processor Storage Unit 8

M67 CR11

Control Register 11 contains channel controller (CC) assignments.

CR11 Channel Controller (CC) partitioning! Bit !! Description
0CC 0 available on CPU 1
1CC 0 available on CPU 2
2-3Reserved for CPUs 3-4
4CC 1 available on CPU 1
5CC 1 available on CPU 2
6-7Reserved for CPUs 3-4
8-15Unassigned
16CPU 1 to only CC 0
17CPU 1 to only CC 1
18-19Reserved for CC 2-3
20CPU 2 to only CC 0
21CPU 2 to only CC 1
22-23Reserved for CC 2-3
24-31Unassigned

M67 CR12

CR12 contains I/O Control Unit Partitioning.

CR12 I/O Control Unit 1-16 Partitioning! Bit !! I/O Control Unit !! Interface
011
12
221
32
431
52
641
72
851
92
1061
112
1271
132
1481
152
1691
172
18101
192
20111
212
22121
232
24131
252
26141
272
28151
292
30161
312

M67 CR13

CR13 contains I/O Control Unit Partitioning.

CR13 I/O Control Unit 17-32 Partitioning ! Bit !! I/O Control Unit !! Interface
0171
12
2181
32
4191
52
6201
72
8211
92
10221
112
12231
132
14241
152
16251
172
18261
192
20271
212
22281
232
24291
252
26301
272
28311
292
30321
312

M67 CR14

CR14 contains indicators.

CR14 Indicators! Bit !! Indicator
0-27Unassigned
222167 Power On
23Unassigned
24Direct Control, CPU 1
25Direct Control, CPU 2
26-27Unassigned
28Prefix, CPU 1
29Prefix, CPU 2
30-31Unassigned

Control registers in IBM S/390

The control registers of ESA/390 on the IBM S/390 are an evolutionary enhancement to the control registers on the earlier ESA/370, S/370-XA and S/370 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.

ESA/390 control registers! CR !! bits !! Field
01SSM-suppression
02TOD-clock-sync control
03Low-address-protection control
04 Extraction-authority control
05Secondary-space control
06Fetch-protection-override control
07Storage-protection-override control
08-12Translation format
013AFP-register control
014Vector control
015Address-space-function control
016Malfunction-alert subclass mask
017Emergency-signal subclass mask
018External-call subclass mask
019TOD-clock sync-check subclass mask
020Clock-comparator subclass mask
021CPU-timer subclass mask
022Service-signal subclass mask
024Set to 1
025Interrupt-key subclass mask
026 Set to 1
027ETR subclass mask
028Program-call-fast
029Crypto control
10Primary space-switch-event control
11-19Primary segment-table origin
122Primary subspace-group control
123Primary private-space control
124Primary storage-alteration-event control
125-31Primary segment-table length
21-25Dispatchable-unit-control-table origin
30-15PSW-key mask
316-31Secondary ASN
4 0-15Authorization index
416-31Primary ASN
50Subsystem-linkage control
51-24Linkage-table origin
525-31Linkage-table length
51-25When the address-space-function control is one,
Primary-ASN-second-table-entry
6 0-7I/O-interruption subclass mask
71-19Secondary segment-table origin
722Secondary subspace-group control
723Secondary private-space control
724Secondary storage-alteration-event control
725-31Secondary segment-table length
80-15Extended authorization index
816-31Monitor masks
90Successful-branching-event mask
91Instruction-fetching-event mask
92Storage-alteration-event mask
93GR-alteration-event mask
94Store-using-real-address-event mask
98Branch-address control
910Storage-alteration-space control
916-31PER general-register masks
101-31PER starting address
111-31PER ending address
120Branch-trace control
121-29Trace-entry address
1230ASN-trace control
1231Explicit-trace control
130Home space-switch-event control
131-19Home segment-table origin
1323Home private-space control
1324Home storage-alteration-event control
1325-31Home segment-table length
140Set to 1
141Set to 1
142Extended-save-area control
143Channel-report-pending subclass mask
144Recovery subclass mask
145Degradation subclass mask
146External-damage subclass mask
147Warning subclass mask
1410TOD-clock-control-override control
14 12 ASN-translation control
1413-31ASN-first-table origin
151-28Linkage-stack-entry address

Control registers in IBM z/Architecture

The control registers of z/Architecture are an evolutionary enhancement to the control registers of the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

z/Architecture mode control registers! CR !! bits !! Field
08Transactional-execution control
09Transactional-execution program-interruption filtering override
010Clock-comparator sign control
013Cryptography counter control
014Processor-activity-instrumentation-extension control
015Measurement-counter-extraction-authorization control
030Warning-track subclass mask
032TRACE TOD-clock control
033SSM-suppression
034TOD-clock-sync control
035Low-address-protection control
036 Extraction-authority control
037Secondary-space control
038Fetch-protection-override control
039Storage-protection-override control
040Enhanced-DAT-enablement control
043Instruction-execution-protection-enablement control
044ASN-and-LX-reuse control
045AFP-register control
046Vector enablement control
048Malfunction-alert subclass mask
048Malfunction-alert subclass mask
049Emergency-signal subclass mask
050External-call subclass mask
052Clock-comparator subclass mask
053CPU-timer subclass mask
054Service-signal subclass mask
056Initialized to 1
057Interrupt-key subclass mask
058Measurement-alert subclass mask
059 Timing-alert subclass mask
061Crypto control
10-51Primary Address-Space Control Element (ASCE)
Primary region-table origin
Primary segment-table origin
Primary real-space token origin
154Primary subspace-group control
155Primary private-space control
156Primary storage-alteration-event
157Primary space-switch-event control
158Primary real-space control
160-61Primary designation-type control
162-63Primary table length
233-57Dispatchable-unit-control-table origin
259Guarded-storage-facility enablement control
261Transaction diagnostic scope
262-63Transaction diagnostic control
30-31Secondary ASN-second-table-entry instance number
332-47PSW-key mask
348-63Secondary ASN
40-31Primary ASN-second-table-entry instance number
4 32-47Authorization index
448-63Primary ASN
533-57Primary-ASN-second-table-entry origin
6 32-39I/O-interruption subclass mask
70-51Secondary Address-Space Control Element (ASCE)
Secondary region-table origin
Secondary segment-table origin
Secondary real-space token origin
754Secondary subspace-group control
755Secondary private-space control
756Secondary storage-alteration-event control
758Secondary real-space control
760-61Secondary designation-type control
762-63Secondary table length
816-31Enhanced-monitor masks
832-47Extended authorization index
848-63Monitor masks
932Successful-branching-event mask
933Instruction-fetching-event mask
934Storage-alteration-event mask
935Storage-key-alteration-event mask
936Store-using-real-address-event mask
937Zero-address-detection-event mask
938Transaction-end event mask
939Instruction-fetching-nullification-event mask
940Branch-address control
941PER-event-suppression control
943Storage-alteration-space control
100-63PER starting address
110-63PER ending address
120Branch-trace control
121Mode-trace control
122-61Trace-entry address
1262ASN-trace control
1263Explicit-trace control
130-51Home Address-Space Control Element (ASCE)
Home region-table origin
Home segment-table origin
Home real-space token origin
1355Home private-space control
1356Home storage-alteration-eventl
1357Home space-switch-event control
1358Secondary real-space control
1360-61Home designation-type control
1362-63Home table length
1432Set to 1
1433Set to 1
1434Extended save-area control (ESA/390-compatibility modeonly)
1435Channel-report-pending subclass mask
1436Recovery subclass mask
1437Degradation subclass mask
1438External-damage subclass mask
1439Warning subclass mask
1442TOD-clock-control-override control
14 44 ASN-translation control
1445-63ASN-first-table origin
150-60Linkage-stack-entry address

Control registers in Intel x86 series

CR0

The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor.

Bit Name Full Name Description
0 PE Protected Mode Enable If 1, system is in protected mode, else, system is in real mode
1 MP Monitor co-processor Controls interaction of WAIT/FWAIT instructions with TS flag in CR0
2 EM Emulation If set, no x87 floating-point unit present, if clear, x87 FPU present
3 TS Task switched Allows saving x87 task context upon a task switch only after x87 instruction used
4 ET Extension type On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387
5 NE Numeric error Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection
16 WP Write protect When set, the CPU cannot write to read-only pages when privilege level is 0
18 AM Alignment mask Alignment check enabled if AM set, AC flag (in EFLAGS register) set, and privilege level is 3
29 NW Not-write through Globally enables/disable write-through caching
30 CD Cache disable Globally enables/disable the memory cache
31 PG Paging If 1, enable paging and use the register, else disable paging.

CR1

Reserved, the CPU will throw a #UD exception when trying to access it.

CR2

Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

CR3

Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for the process-context identifier (PCID).[2]

CR4

Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions.

Bit Name Full Name Description
0 VME If set, enables support for the virtual interrupt flag (VIF) in virtual-8086 mode.
1 PVI Protected-mode Virtual Interrupts If set, enables support for the virtual interrupt flag (VIF) in protected mode.
2 TSD Time Stamp Disable If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level.
3 DE Debugging Extensions If set, enables debug register based breaks on I/O space access.
4 PSE If set, enables 32-bit paging mode to use 4 MiB huge pages in addition to 4 KiB pages.If PAE is enabled or the processor is in x86-64 long mode this bit is ignored.[3]
5 PAE If set, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses.
6 MCE Machine Check Exception If set, enables machine check interrupts to occur.
7 PGE Page Global Enabled If set, address translations (PDE or PTE records) may be shared between address spaces.
8 PCE Performance-Monitoring Counter enable If set, RDPMC can be executed at any privilege level, else RDPMC can only be used in ring 0.
9 OSFXSR Operating system support for FXSAVE and FXRSTOR instructions If set, enables Streaming SIMD Extensions (SSE) instructions and fast FPU save & restore.
10 OSXMMEXCPT Operating System Support for Unmasked SIMD Floating-Point Exceptions If set, enables unmasked SSE exceptions.
11 UMIP User-Mode Instruction Prevention If set, the SGDT, SIDT, SLDT, SMSW and STR instructions cannot be executed if CPL > 0.
12 LA57 57-Bit Linear Addresses If set, enables 5-Level Paging.[4] [5]
13 VMXE Virtual Machine Extensions Enable see Intel VT-x x86 virtualization.
14 SMXE Safer Mode Extensions Enable see Trusted Execution Technology (TXT)
15
16 FSGSBASE FSGSBASE Enable If set, enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
17 PCIDE PCID Enable If set, enables process-context identifiers (PCIDs).
18 OSXSAVE XSAVE and Processor Extended States Enable
19 KL Key Locker Enable If set, enables the AES Key Locker instructions.
20 [6] Supervisor Mode Execution Protection Enable If set, execution of code in a higher ring generates a fault.
21 SMAP Supervisor Mode Access Prevention Enable If set, access of data in a higher ring generates a fault.[7]
22 PKE Protection Key Enable See Intel 64 and IA-32 Architectures Software Developer's Manual.
23 CET Control-flow Enforcement Technology If set, enables control-flow enforcement technology.
24 PKS Enable Protection Keys for Supervisor-Mode Pages If set, each supervisor-mode linear address is associated with a protection key when 4-level or 5-level paging is in use.
25 UINTR User Interrupts Enable If set, enables user-mode inter-processor interrupts and their associated instructions and data structures.
63-26

CR5–7

Reserved, same case as CR1.

Additional Control registers in Intel x86-64 series

EFER

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080.

BitPurpose
0SCE (System Call Extensions)
1DPE (AMD K6 only: Data Prefetch Enable)
2SEWBED (AMD K6 only: Speculative EWBE# Disable)
3GEWBED (AMD K6 only: Global EWBE# Disable)
4L2D (AMD K6 only: L2 Cache Disable)
5-7Reserved, Read as Zero
8LME (Long Mode Enable)
9Reserved
10LMA (Long Mode Active)
11NXE (No-Execute Enable)
12SVME (Secure Virtual Machine Enable)
13LMSLE (Long Mode Segment Limit Enable)
14FFXSR (Fast FXSAVE/FXRSTOR)
15TCE (Translation Cache Extension)
16Reserved
17MCOMMIT (MCOMMIT instruction enable)
18INTWB (Interruptible WBINVD/WBNOINVD enable)
19Reserved
20UAIE (Upper Address Ignore Enable)
21AIBRSE (Automatic IBRS Enable)
22–63Reserved

CR8

CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).[3]

The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.

System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.

The TPR is cleared to 0 on reset.

XCR0 and XSS

XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be changed using the privileged XSETBV read using the unprivileged XGETBV instructions.[8]

BitNameEnabled FeaturePurpose
0X87x87 FPUx87 FPU/MMX State, must be '1'
1SSESSEMXCSR and 16 XMM registers
2AVXAVX16 upper-halves of the YMM registers
3BNDREGMPXFour BND registers
4BNDCSRBNDCFGU and BNDSTATUS registers
5OPMASKAVX-512Eight k-mask registers
6ZMM_Hi25616 upper-halves of the ZMM registers
7Hi16_ZMM16 "high" ZMM registers (ZMM16 through ZMM31)
8PTProcessor Trace
9PKRUProtection KeysPKRU register
10PASID
11CET_UIntel CETUser shadow stack
12CET_SSupervisor shadow stack
13HDCHardware Duty Cycling
14UINTRUser interrupts
15LBRLast Branch Records
16HWPHardware P-states
17XTILECFGIntel AMX64-byte TILECFG register
18XTILEDATAEight 1024-byte TILE registers
19APXIntel APX16 "high" GPRs (R16 through R31)
20–63Reserved

There is also the IA32_XSS MSR, which is located at address DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.

BitPurpose
0–7Reserved; must be 0.
8PT (Enables the saving and loading of nine Processor Trace MSRs.)
10Processor Address Space ID (PASID) state
11Control-flow Enforcement Technology (CET) User State
12Control-flow Enforcement Technology (CET) Supervisor State
13HDC (Enables the saving and loading of the IA32_PM_CTL1 MSR.)
14User interrupts (UINTR) state
15Last branch recording (LBR) state
16HWP (enables the saving/loading of IA32_HWP_REQUEST MSR)
17–63Reserved; must be 0.

See also

References

IBM manuals
  • M67prelim
  • Book: System/360 Model 67 - Time Sharing System - Preliminary Technical Summary . C20-1647-0 . . First . . Systems Reference Library . May 8, 2023 .
    M67
  • Book: IBM System/360 Model 67 - Functional Characteristics . A27-2719-0 . . February 1972 . Third . . Systems Reference Library . May 8, 2023 .
    S/370
  • Book: IBM System/370 - Principles of Operation . GA22-7000-10 . . September 1987 . Eleventh . . May 8, 2023 .
    S/370-XA
  • Book: IBM System/370 Extended Architecture Principles of Operation . SA22-7085-1 . January 1987 . Second . . . May 8, 2023 .
    S/370-ESA
  • Book: IBM Enterprise Systems Architecture/370 Principles of Operation . SA22-7200-0 . August 1988 . First . . . May 8, 2023 .
    S/390-ESA
  • Book: IBM Enterprise Systems Architecture/390 Principles of Operation . SA22-7201-08 . June 2003 . Ninth . . . May 8, 2023.
    z/Architecture
  • Book: z/Architecture - Principles of Operation . SA22-7832-13 . May 2022 . Fourteenth . . . May 8, 2023.

    External links

    Notes and References

    1. Web site: March 17, 2024 . lab4.pdf . live . https://web.archive.org/web/20210117180151/https://www.it.uu.se/edu/course/homepage/mil/vt13/labcourse/lab4.pdf . January 17, 2021 . March 16, 2024 . Uppsala University.
    2. Book: Intel 64 and IA-32 Architectures Software Developer's Manual . 3A: System Programming Guide, Part 1 . 4.10.1 Process-Context Identifiers (PCIDs) . Intel Corporation . 2016 .
    3. Web site: AMD64 Architecture Programmer's Manual Volume 2: System Programming . . September 2012 . 127 & 130 . 2017-08-04.
    4. Web site: 5-Level Paging and 5-Level EPT . . May 2017 . 16 . 2018-01-23.
    5. Web site: Intel 64 and IA-32 Architectures Software Developer's Manual . 3A . Intel® Corporation . 2021-06-28 . 2021-09-21 .
    6. Web site: Supervisor Mode Execution Protection . Stephen . Fischer . 2011-09-21 . NSA Trusted Computing Conference 2011 . National Conference Services, Inc. . https://web.archive.org/web/20160803075007/https://www.ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf . 2016-08-03 . dead . 2017-08-04 .
    7. Web site: x86: Supervisor Mode Access Prevention . Anvin . H. Peter . 2012-09-21 . . 2017-08-04.
    8. Web site: Chapter 13, Managing State Using The Xsave Feature Set . Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture . Intel Corporation (2019) . 23 March 2019.

    This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "Control register".

    Except where otherwise indicated, Everything.Explained.Today is © Copyright 2009-2024, A B Cryer, All Rights Reserved. Cookie policy.