The Configurable Fault Tolerant Processor (CFTP), developed by the Space Systems Academic Group at the Naval Postgraduate School, is an experimental payload on board the United States Naval Academy's (USNA) MidSTAR-1 satellite. Midstar-1 was launched into a 492km low Earth orbit (LEO) on March 8, 2007, aboard an Atlas V expendable launch vehicle from Cape Canaveral Air Force Station, along with FalconSat 3, STPSat 1, and CFESat as secondary payloads. The primary payload was Orbital Express.
The Configurable Fault Tolerant Processor Project aims to demonstrate the feasibility of using Field Programmable Gate Arrays (FPGAs) for spacecraft computer processing by applying various fault tolerance techniques to the designs. CFTP provides a valuable testbed for on-orbit evaluation of various fault tolerant concepts.
The use of FPGAs provides added flexibility, allowing on-orbit upgrades and rapid development cycles. Using Commercial off the shelf (COTS) technology allows the engineer to produce more technologically advanced designs at a lower cost and in a shorter time than using more traditional space-grade components.
Space-based FPGA design also provides the Naval Postgraduate School students with unique challenges in developing for and configuring the system. Remotely accessing the platform over a limited downlink and uplink provides challenges not seen on ground-based systems.[1]
The CFTP-1 board utilizes Xilinx Virtex I parts for both the control and experiment FPGAs. The complete CFTP payload, as delivered to MidSTAR-1, consists of the CFTP board itself (shown in the spacecraft image above), an ARM processor board that communicates with the control FPGA on the CFTP board through a PC/104 bus, and a power supply board. The ARM processor board communicates with the spacecraft's Command and Data Handler (C&DH) computer through a serial PPP link.
CFTP-1 underwent radiation testing at the UC Davis' cyclotron facility prior to integration with the MidSTAR satellite.
The CFTP-2 system is currently an entirely ground based system. The CFTP-2 board itself is set up nearly identically to the CFTP-1 board, however it utilizes a Xilinx Virtex 2 part as the experiment FPGA, rather than the Xilinx Virtex I part on CFTP-1. This system was tested in a proton beam using the University of California at Davis' cyclotron.