CUDA explained

CUDA
Developer:	Nvidia
Latest Release Version:	12.6
Operating System:	Windows, Linux
Platform:	Supported GPUs
Genre:	GPGPU
License:	Proprietary

In computing, CUDA (originally Compute Unified Device Architecture) is a proprietary^[1] parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, an approach called general-purpose computing on GPUs (GPGPU). CUDA API and its runtime: The CUDA API is an extension of the C programming language that adds the ability to specify thread-level parallelism in C and also to specify GPU device specific operations (like moving data between the CPU and the GPU).^[2] CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements for the execution of compute kernels.^[3] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

CUDA is designed to work with programming languages such as C, C++, Fortran and Python. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which required advanced skills in graphics programming.^[4] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL.^[5]

CUDA was created by Nvidia in 2006.^[6] When it was first introduced, the name was an acronym for Compute Unified Device Architecture,^[7] but Nvidia later dropped the common use of the acronym and no longer uses it.

Background

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

• cryptographic hash functions
• machine learning
• molecular dynamics simulations
• physics engines

Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2006. Around 2015, the focus of CUDA changed to neural networks.^[8]

Ontology

The following table offers a non-exact description for the ontology of CUDA framework.

The ontology of CUDA framework! memory (hardware) ! memory (code, or variable scoping) ! computation (hardware) ! computation (code syntax) ! computation (code semantics)

RAM	non-CUDA variables	host	program	one routine call
VRAM, GPU L2 cache	global, const, texture	device	grid	simultaneous call of the same subroutine on many processors
GPU L1 cache	local, shared	SM ("streaming multiprocessor")	block	individual subroutine call
		warp = 32 threads		SIMD instructions
GPU L0 cache, register		thread (aka. "SP", "streaming processor", "cuda core", but these names are now deprecated)		analogous to individual scalar ops within a vector op

Programming abilities

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself.^[9] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group. Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL, Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP. Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more.^{[10] [11] [12] [13] [14]}

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,^[15] which supersedes the beta released February 14, 2008.^[16] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

• cuBLAS – CUDA Basic Linear Algebra Subroutines library
• CUDART – CUDA Runtime library
• cuFFT – CUDA Fast Fourier Transform library
• cuRAND – CUDA Random Number Generation library
• cuSOLVER – CUDA based collection of dense and sparse direct solvers
• cuSPARSE – CUDA Sparse Matrix library
• NPP – NVIDIA Performance Primitives library
• nvGRAPH – NVIDIA Graph Analytics library
• NVML – NVIDIA Management Library
• NVRTC – NVIDIA Runtime Compilation library for CUDA C++

CUDA 8.0 comes with these other software components:

• nView – NVIDIA nView Desktop Management Software
• NVWMI – NVIDIA Enterprise Management Toolkit
• GameWorks PhysX – is a multi-platform game physics engine

CUDA 9.0–9.2 comes with these other components:

• CUTLASS 1.0 – custom linear algebra algorithms,
• NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK

CUDA 10 comes with these other components:

• nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:^{[17] [18] [19] [20]}

• CUB is new one of more supported C++ libraries
• MIG multi instance GPU support
• nvJPEG2000 – JPEG 2000 encoder and decoder

Advantages

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

• Scattered readscode can read from arbitrary addresses in memory.
• Unified virtual memory (CUDA 4.0 and above)
• Unified memory (CUDA 6.0 and above)
• Shared memoryCUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.^[21]
• Faster downloads and readbacks to and from the GPU
• Full support for integer and bitwise operations, including integer texture lookups

Limitations

• Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.^[22] This was not always the case. Earlier versions of CUDA were based on C syntax rules.^[23] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
• Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
• Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
• Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
• No emulation or fallback functionality is available for modern revisions.
• Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.
• C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
• In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.^[24]
• Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.^[25] Attempts to implement CUDA on other GPUs include:
  • Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.^{[26] [27] [28]}
  • CU2CL: Convert CUDA 3.2 C++ to OpenCL C.^[29]
  • GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
  • ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.^[30] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.
  • chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.^[31]

Example

This example code in C++ loads a texture from an image into an array on the GPU:

texture tex;

void foo //end foo

__global__ void kernel(float* odata, int height, int width)

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.^[32] import pycuda.compiler as compimport pycuda.driver as drvimport numpyimport pycuda.autoinit

mod = comp.SourceModule("""__global__ void multiply_them(float *dest, float *a, float *b)""")

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)multiply_them(drv.Out(dest), drv.In(a), drv.In(b), block=(400, 1, 1))

print(dest - a * b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.^[33]

import numpyfrom pycublas import CUBLASMatrix

A = CUBLASMatrix(numpy.mat(1, 2, 3, [4, 5, 6]], numpy.float32))B = CUBLASMatrix(numpy.mat(2, 3, [4, 5], [6, 7]], numpy.float32))C = A * Bprint(C.np_mat)

while CuPy directly replaces NumPy:^[34]

import cupy

a = cupy.random.randn(400)b = cupy.random.randn(400)

dest = cupy.zeros_like(a)

print(dest - a * b)

GPUs supported

Supported CUDA Compute Capability versions for CUDA SDK version and Microarchitecture (by code name):

Compute Capability (CUDA SDK support vs. Microarchitecture)

CUDA SDK Version(s)			Kepler (Early)	Kepler (Late)								Blackwell
1.0^[35]
1.1
2.0
2.1 – 2.3.1^[36] ^[37] ^[38] ^[39]
3.0 – 3.1^[40] ^[41]
3.2^[42]
4.0 – 4.2
5.0 – 5.5
6.0
6.5
7.0 – 7.5
8.0
9.0 – 9.2
10.0 – 10.2
11.0^[43]
11.1 – 11.4^[44]
11.5 – 11.7.1^[45]
11.8^[46]
12.0 – 12.5

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA Compute Capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

Compute Capability, GPU semiconductors and Nvidia GPU board products

Compute capability (version)	Micro- architecture	GPUs	GeForce	Quadro, NVS	Tesla/Datacenter	Tegra, Jetson, DRIVE
1.0	Tesla	G80	GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80)	Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4	Tesla C870, Tesla D870, Tesla S870
1.1		G92, G94, G96, G98, G84, G86	GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT, GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M	Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4, Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420,^[47] Quadro NVS 295
1.2		GT218, GT216, GT215	GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210, GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M	Quadro FX 380 Low Profile, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M, Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION
1.3		GT200, GT200b	GeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260	Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2	Tesla C1060, Tesla S1070, Tesla M1060
2.0	Fermi	GF100, GF110	GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465, GeForce GTX 480M	Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000, Quadro 5010M, Quadro 5000M	Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090
2.1		GF104, GF106 GF108, GF114, GF116, GF117, GF119	GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*, GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M	Quadro 2000, Quadro 2000D, Quadro 600, Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M, NVS 310, NVS 315, NVS 5400M, NVS 5200M, NVS 4200M
3.0	Kepler	GK104, GK106, GK107	GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650, GeForce GTX 880M, GeForce GTX 870M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M	Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420, Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M, NVS 510, Quadro 410	Tesla K10, GRID K340, GRID K520, GRID K2
3.2		GK20A				Tegra K1, Jetson TK1
3.5		GK110, GK208	GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710, GeForce GT 740M (64-bit, DDR3), GeForce GT 920M	Quadro K6000, Quadro K5200	Tesla K40, Tesla K20x, Tesla K20
3.7		GK210			Tesla K80
5.0	Maxwell	GM107, GM108	GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830M	Quadro K1200, Quadro K2200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M, NVS 810	Tesla M10
5.2		GM200, GM204, GM206	GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE, GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M	Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500, Quadro M5000M, Quadro M4000M, Quadro M3000M	Tesla M4, Tesla M40, Tesla M6, Tesla M60
5.3		GM20B				Tegra X1, Jetson TX1, Jetson Nano, DRIVE CX, DRIVE PX
6.0	Pascal	GP100		Quadro GP100	Tesla P100
6.1		GP102, GP104, GP106, GP107, GP108	Nvidia TITAN Xp, Titan X, GeForce GTX 1080 Ti, GTX 1080, GTX 1070 Ti, GTX 1070, GTX 1060, GTX 1050 Ti, GTX 1050, GT 1030, GT 1010, MX350, MX330, MX250, MX230, MX150, MX130, MX110	Quadro P6000, Quadro P5000, Quadro P4000, Quadro P2200, Quadro P2000, Quadro P1000, Quadro P400, Quadro P500, Quadro P520, Quadro P600, Quadro P5000(Mobile), Quadro P4000(Mobile), Quadro P3000(Mobile)	Tesla P40, Tesla P6, Tesla P4
6.2		GP10B^[48]				Tegra X2, Jetson TX2, DRIVE PX 2
7.0	Volta	GV100	NVIDIA TITAN V	Quadro GV100	Tesla V100, Tesla V100S
7.2		GV10B^[49] GV11B^[50] ^[51]				Tegra Xavier, Jetson Xavier NX, Jetson AGX Xavier, DRIVE AGX Xavier, DRIVE AGX Pegasus, Clara AGX
7.5	Turing	TU102, TU104, TU106, TU116, TU117	NVIDIA TITAN RTX, GeForce RTX 2080 Ti, RTX 2080 Super, RTX 2080, RTX 2070 Super, RTX 2070, RTX 2060 Super, RTX 2060 12GB, RTX 2060, GeForce GTX 1660 Ti, GTX 1660 Super, GTX 1660, GTX 1650 Super, GTX 1650, MX550, MX450	Quadro RTX 8000, Quadro RTX 6000, Quadro RTX 5000, Quadro RTX 4000, T1000, T600, T400 T1200(mobile), T600(mobile), T500(mobile), Quadro T2000(mobile), Quadro T1000(mobile)	Tesla T4
8.0	Ampere	GA100			A100 80GB, A100 40GB, A30
8.6		GA102, GA103, GA104, GA106, GA107	GeForce RTX 3090 Ti, RTX 3090, RTX 3080 Ti, RTX 3080 12GB, RTX 3080, RTX 3070 Ti, RTX 3070, RTX 3060 Ti, RTX 3060, RTX 3050, RTX 3050 Ti(mobile), RTX 3050(mobile), RTX 2050(mobile), MX570	RTX A6000, RTX A5500, RTX A5000, RTX A4500, RTX A4000, RTX A2000 RTX A5000(mobile), RTX A4000(mobile), RTX A3000(mobile), RTX A2000(mobile)	A40, A16, A10, A2
8.7		GA10B				Jetson Orin Nano, Jetson Orin NX, Jetson AGX Orin, DRIVE AGX Orin, DRIVE AGX Pegasus OA, Clara Holoscan
8.9	Ada Lovelace^[52]	AD102, AD103, AD104, AD106, AD107	GeForce RTX 4090, RTX 4080 Super, RTX 4080, RTX 4070 Ti Super, RTX 4070 Ti, RTX 4070 Super, RTX 4070, RTX 4060 Ti, RTX 4060	RTX 6000 Ada, RTX 5880 Ada, RTX 5000 Ada, RTX 4500 Ada, RTX 4000 Ada, RTX 4000 SFF	L40S, L40, L20, L4, L2
9.0	Hopper	GH100			H200, H100
10.0	Blackwell	GB100			B200, B100
10.x		GB202, GB203, GB205, GB206, GB207	GeForce RTX 5090, RTX 5080		B40
Compute capability (version)	Micro- architecture	GPUs	GeForce	Quadro, NVS	Tesla/Datacenter	Tegra, Jetson, DRIVE

'

• ' – OEM-only products

Version features and specifications

Feature support (unlisted features are supported for all compute capabilities)	Compute capability (version)
	1.0, 1.1	1.2, 1.3	2.x	3.0	3.2	3.5, 3.7, 5.x, 6.x, 7.0, 7.2	7.5	8.x	9.0
Warp vote functions (__all, __any)	colspan="8"
Warp vote functions (__ballot)	colspan="7" rowspan="5"
Memory fence functions (__threadfence_system)
Synchronization functions (__syncthreads_count, __syncthreads_and, __syncthreads_or)
Surface functions
3D grid of thread blocks
Warp shuffle functions	colspan="6" rowspan="2"
Unified memory programming
Funnel shift	colspan="5" rowspan="1"
Dynamic parallelism	colspan="4" rowspan="1"
Uniform Datapath^[53]	colspan="3" rowspan="1"
Hardware-accelerated async-copy	colspan="2" rowspan="4"
Hardware-accelerated split arrive/wait barrier
Warp-level support for reduction ops
L2 cache residency management
DPX instructions for accelerated dynamic programming	colspan="1" rowspan="4"
Distributed shared memory
Thread block cluster
Tensor memory accelerator (TMA) unit
Feature support (unlisted features are supported for all compute capabilities)	1.0,1.1	1.2,1.3	2.x	3.0	3.2	3.5, 3.7, 5.x, 6.x, 7.0, 7.2	7.5	8.x	9.0
	Compute capability (version)

^[54]

Data types

Data type	Operation	Supported since	Atomic Operation	Supported since for global memory	Supported since for shared memory
8-bit integer signed/unsigned	loading, storing, conversion			colspan="2"
16-bit integer signed/unsigned	general operations		atomicCAS	colspan="2"
32-bit integer signed/unsigned	general operations		atomic functions
64-bit integer signed/unsigned	general operations		atomic functions
any 128-bit trivially copyable type	general operations		atomicExch, atomicCAS	colspan="2"
16-bit floating point FP16	addition, subtraction, multiplication, comparison, warp shuffle functions, conversion	half2 atomic addition	colspan="2"
			atomic addition	colspan="2"
16-bit floating point BF16	addition, subtraction, multiplication, comparison, warp shuffle functions, conversion		atomic addition	colspan="2"
32-bit floating point	general operations	atomicExch
			atomic addition	colspan="2"
32-bit floating point float2 and float4	general operations		atomic addition	colspan="2"
64-bit floating point	general operations		atomic addition

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.^[55]

Tensor cores

FMA per cycle per tensor core^[56]	Supported since		7.0	7.2	7.5 Workstation	7.5 Desktop	8.0	8.6 Workstation	8.7	8.9 Workstation	8.6 Desktop	8.9 Desktop	9.0	10.0
Data Type	For dense matrices	For sparse matrices			colspan="1"
1-bit values (AND)		colspan="2"
1-bit values (XOR)	rowspan="2" colspan="2"
4-bit integers		colspan="1"
4-bit floating point FP4 (E2M1?)	colspan="1"
6-bit floating point FP6 (E3M2 and E2M3?)	colspan="1"
8-bit integers				rowspan="3"
8-bit floating point FP8 (E4M3 and E5M2) with FP16 accumulate	rowspan="2" colspan="1"
8-bit floating point FP8 (E4M3 and E5M2) with FP32 accumulate
16-bit floating point FP16 with FP16 accumulate		rowspan="3"
16-bit floating point FP16 with FP32 accumulate	rowspan="2"
16-bit floating point BF16 with FP32 accumulate	rowspan="3" colspan="2"
32-bit (19 bits used) floating point TF32
64-bit floating point

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.^{[57] [58] [59] [60] [61] [62]}

Tensor Core Composition	7.0	7.2, 7.5	8.0, 8.6	8.7	8.9	9.0
Dot Product Unit Width in FP16 units (in bytes)^[63] ^[64] ^[65] ^[66]
Dot Product Units per Tensor Core	colspan="4"
Tensor Cores per SM partition	colspan="4"
Full throughput (Bytes/cycle)^[67] per SM partition^[68]		colspan="1"
FP Tensor Cores: Minimum cycles for warp-wide matrix calculation
FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)^[69]
INT Tensor Cores: Minimum cycles for warp-wide matrix calculation
INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)

^{[70] [71] [72] [73]}

FP64 Tensor Core Composition	8.0	8.6	8.7	8.9	9.0
Dot Product Unit Width in FP64 units (in bytes)		colspan="1"
Dot Product Units per Tensor Core		colspan="1"
Tensor Cores per SM partition	colspan="5"
Full throughput (Bytes/cycle)^[74] per SM partition^[75]		colspan="1"
Minimum cycles for warp-wide matrix calculation
Minimum Matrix Shape for full throughput (Bytes)^[76]

Technical Specification

Technical specifications	Compute capability (version)
	1.0	1.1	1.2	1.3	2.x	3.0	3.2	3.5	3.7	5.0	5.2	5.3	6.0	6.1	6.2	7.0	7.2	7.5	8.0	8.6	8.7	8.9	9.0
Maximum number of resident grids per device (concurrent kernel execution, can be lower for specific devices)	colspan="6"
Maximum dimensionality of grid of thread blocks	colspan="19"
Maximum x-dimension of a grid of thread blocks	colspan="18"
Maximum y-, or z-dimension of a grid of thread blocks	colspan="23"
Maximum dimensionality of thread block	colspan="23"
Maximum x- or y-dimension of a block	colspan="19"
Maximum z-dimension of a block	colspan="23"
Maximum number of threads per block	colspan="19"
Warp size	colspan="23"
Maximum number of resident blocks per multiprocessor	colspan="1"
Maximum number of resident warps per multiprocessor	colspan="1"
Maximum number of resident threads per multiprocessor	colspan="1"
Number of 32-bit regular registers per multiprocessor	colspan="14"
Number of 32-bit uniform registers per multiprocessor	colspan="1" ^[77] ^[78]																	colspan="5"
Maximum number of 32-bit registers per thread block	colspan="8"
Maximum number of 32-bit regular registers per thread	colspan="17"
Maximum number of 32-bit uniform registers per warp	colspan="1" ^[79] ^[80]																	colspan="5"
Amount of shared memory per multiprocessor (out of overall shared memory + L1 cache, where applicable)	colspan="1"
Maximum amount of shared memory per thread block	colspan="1"
Number of shared memory banks	colspan="19"
Amount of local memory per thread	colspan="19"
Constant memory size accessible by CUDA C/C++ (1 bank, PTX can access 11 banks, SASS can access 18 banks)	colspan="23"
Cache working set per multiprocessor for constant memory	colspan="10"
Cache working set per multiprocessor for texture memory	colspan="1"
Maximum width for 1D texture reference bound to a CUDA array	colspan="11"
Maximum width for 1D texture reference bound to linear memory	colspan="6"
Maximum width and number of layers for a 1D layered texture reference	colspan="11"
Maximum width and height for 2D texture reference bound to a CUDA array	colspan="11"
Maximum width and height for 2D texture reference bound to a linear memory	colspan="11"
Maximum width and height for 2D texture reference bound to a CUDA array supporting texture gather	colspan="11"
Maximum width, height, and number of layers for a 2D layered texture reference	colspan="11"
Maximum width, height and depth for a 3D texture reference bound to linear memory or a CUDA array	colspan="11"
Maximum width (and height) for a cubemap texture reference	colspan="11"
Maximum width (and height) and number of layers for a cubemap layered texture reference	colspan="11"
Maximum number of textures that can be bound to a kernel	colspan="18"
Maximum width for a 1D surface reference bound to a CUDA array	colspan="11"
Maximum width and number of layers for a 1D layered surface reference	colspan="11"
Maximum width and height for a 2D surface reference bound to a CUDA array	colspan="11"
Maximum width, height, and number of layers for a 2D layered surface reference	colspan="11"
Maximum width, height, and depth for a 3D surface reference bound to a CUDA array	colspan="11"
Maximum width (and height) for a cubemap surface reference bound to a CUDA array	colspan="11"
Maximum width and number of layers for a cubemap layered surface reference	colspan="11"
Maximum number of surfaces that can be bound to a kernel	colspan="8"
Maximum number of instructions per kernel	colspan="19"
Maximum number of Thread Blocks per Thread Block Cluster^[81]
Technical specifications	1.0	1.1	1.2	1.3	2.x	3.0	3.2	3.5	3.7	5.0	5.2	5.3	6.0	6.1	6.2	7.0	7.2	7.5	8.0	8.6	8.7	8.9	9.0
	Compute capability (version)

^{[82] [83]}

Multiprocessor Architecture

Architecture specifications	Compute capability (version)
	1.0	1.1	1.2	1.3	2.0	2.1	3.0	3.2	3.5	3.7	5.0	5.2	5.3	6.0	6.1	6.2	7.0	7.2	7.5	8.0	8.6	8.7	8.9	9.0
Number of ALU lanes for INT32 arithmetic operations	colspan="2"
Number of ALU lanes for any INT32 or FP32 arithmetic operation	colspan="2"
Number of ALU lanes for FP32 arithmetic operations	rowspan="2" colspan="1"
Number of ALU lanes for FP16x2 arithmetic operations	rowspan="1" colspan="1"
Number of ALU lanes for FP64 arithmetic operations
Number of Load/Store Units	colspan="1"
Number of special function units for single-precision floating-point transcendental functions	colspan="8"
Number of texture mapping units (TMU)	colspan="8"
Number of ALU lanes for uniform INT32 arithmetic operations	colspan="5"
Number of tensor cores		colspan="2"
Number of raytracing cores																						colspan="1"
Number of SM Partitions = Processing Blocks^[84]	colspan="10"
Number of warp schedulers per SM partition	colspan="14"
Max number of new instructions issued each cycle by a single scheduler^[85]	colspan="8"
Size of unified memory for data cache and shared memory	^[86]
Size of L3 instruction cache per GPU				^[87]			colspan="18" rowspan="2"
Size of L2 instruction cache per Texture Processor Cluster (TPC)
Size of L1.5 instruction cache per SM^[88]											^[89]
Size of L1 instruction cache per SM
Size of L0 instruction cache per SM partition			^[90]
Instruction Width^[91]	colspan="8"
Memory Bus Width per Memory Partition in bits
L2 Cache per Memory Partition	colspan="1"
Number of Render Output Units (ROP) per memory partition (or per GPC in later models)	colspan="2"
Architecture specifications	1.0	1.1	1.2	1.3	2.0	2.1	3.0	3.2	3.5	3.7	5.0	5.2	5.3	6.0	6.1	6.2	7.0	7.2	7.5	8.0	8.6	8.7	8.9	9.0
	Compute capability (version)

^[92]

For more information read the Nvidia CUDA programming guide.^[93]

Current and future usages of CUDA architecture

• Accelerated rendering of 3D graphics
• Accelerated interconversion of video file formats
• Accelerated encryption, decryption and compression
• Bioinformatics, e.g. NGS DNA sequencing BarraCUDA^[94]
• Distributed calculations, such as predicting the native conformation of proteins
• Medical analysis simulations, for example virtual reality based on CT and MRI scan images
• Physical simulations,^[95] in particular in fluid dynamics
• Neural network training in machine learning problems
• Large Language Model inference
• Face recognition
• Volunteer computing projects, such as SETI@home and other projects using BOINC software
• Molecular dynamics
• Mining cryptocurrencies
• Structure from motion (SfM) software

Comparison with competitors

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

Intel OneAPI

See main article: OneAPI (compute acceleration).

oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.^[96] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implemente their own versions of oneAPI libraries.^{[97] [98]}

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

Unified Acceleration Foundation (UXL)

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.^[99]

AMD ROCm

See main article: ROCm.

ROCm^[100] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

See also

• SYCL – an open standard from Khronos Group for programming a variety of platforms, including GPUs, with single-source modern C++, similar to higher-level CUDA Runtime API (single-source)
• BrookGPU – the Stanford University graphics group's compiler
• Array programming
• Parallel computing
• Stream processing
• rCUDA – an API for computing on remote computers
• Molecular modeling on GPUs
• Vulkan – low-level, high-performance 3D graphics and computing API
• OptiX – ray tracing API by NVIDIA
• CUDA binary (cubin) – a type of fat binary
• Numerical Library Collection – by NEC for their vector processor

Further reading

• Buck . Ian . Foley . Tim . Horn . Daniel . Sugerman . Jeremy . Fatahalian . Kayvon . Houston . Mike . Hanrahan . Pat . 2004-08-01 . Brook for GPUs: stream computing on graphics hardware . ACM Transactions on Graphics . 23 . 3 . 777–786 . 10.1145/1015706.1015800 . 0730-0301.
• Nickolls . John . Buck . Ian . Garland . Michael . Skadron . Kevin . 2008-03-01 . Scalable Parallel Programming with CUDA: Is CUDA the parallel programming model that application developers have been waiting for? . Queue . 6 . 2 . 40–53 . 10.1145/1365490.1365500 . 1542-7730.

External links

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Notes and References

1. Web site: Shah . Agam . Nvidia not totally against third parties making CUDA chips . 2024-04-25 . www.theregister.com . en.
2. Web site: Nvidia . What is CUDA? . Nvidia . 21 March 2024.
3. Web site: Nvidia's CUDA: The End of the CPU? . Abi-Chahla . Fedy . June 18, 2008 . Tom's Hardware . May 17, 2015.
4. News: CUDA vs. OpenCL vs. OpenGL . Zunitch . Peter . 2018-01-24 . Videomaker . 2018-09-16 . en-US.
5. Web site: OpenCL . 2013-04-24 . NVIDIA Developer . en . 2019-11-04.
6. Web site: 18 July 2017 . Nvidia CUDA Home Page .
7. Web site: Nvidia's GeForce 8800 (G80): GPUs Re-architected for DirectX 10 . Shimpi . Anand Lal . Wilson . Derek . November 8, 2006 . AnandTech . May 16, 2015.
8. Witt . Stephen . 2023-11-27 . How Jensen Huang's Nvidia Is Powering the A.I. Revolution . en-US . The New Yorker . 2023-12-10 . 0028-792X.
9. Web site: CUDA LLVM Compiler. 7 May 2012.
10. Book: Vasiliadis . Giorgos . Antonatos . Spiros . Polychronakis . Michalis . Markatos . Evangelos P. . Ioannidis . Sotiris . Recent Advances in Intrusion Detection . Gnort: High Performance Network Intrusion Detection Using Graphics Processors . Lecture Notes in Computer Science . September 2008 . 5230 . 116–134 . 10.1007/978-3-540-87403-4_7 . 978-3-540-87402-7 . http://www.ics.forth.gr/dcs/Activities/papers/gnort.raid08.pdf .
11. Schatz . Michael C. . Trapnell . Cole . Delcher . Arthur L. . Varshney . Amitabh . 2007 . High-throughput sequence alignment using Graphics Processing Units . BMC Bioinformatics . 8. 10.1186/1471-2105-8-474 . 474 . 18070356 . 2222658 . free .
12. Manavski . Svetlin A. . Giorgio . Valle . CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment . BMC Bioinformatics . 10 . 2008 . Suppl 2 . 10.1186/1471-2105-9-S2-S10 . S10 . 18387198 . 2323659 . free .
13. Web site: Pyrit – Google Code.
14. Web site: Use your Nvidia GPU for scientific computing. https://web.archive.org/web/20081228022142/http://boinc.berkeley.edu/cuda.php. 2008-12-28. dead. 2017-08-08. BOINC. 2008-12-18.
15. Web site: Nvidia CUDA Software Development Kit (CUDA SDK) – Release Notes Version 2.0 for MAC OS X. dead. https://web.archive.org/web/20090106020401/http://developer.download.nvidia.com/compute/cuda/sdk/website/doc/CUDA_SDK_release_notes_macosx.txt. 2009-01-06.
16. Web site: CUDA 1.1 – Now on Mac OS X. February 14, 2008. dead. https://web.archive.org/web/20081122105633/http://news.developer.nvidia.com/2008/02/cuda-11---now-o.html. November 22, 2008.
17. Web site: CUDA 11 Features Revealed. 14 May 2020.
18. Web site: CUDA Toolkit 11.1 Introduces Support for GeForce RTX 30 Series and Quadro RTX Series GPUs. 23 September 2020.
19. Web site: Enhancing Memory Allocation with New NVIDIA CUDA 11.2 Features. 16 December 2020.
20. Web site: Exploring the New Features of CUDA 11.3. 16 April 2021.
21. 10.1145/1375527.1375572. Efficient computation of sum-products on GPUs through software-managed cache. Proceedings of the 22nd annual international conference on Supercomputing – ICS '08. 2008. Silberstein. Mark. Schuster. Assaf. Assaf Schuster . Geiger. Dan. Patney. Anjul. Owens. John D.. Proceedings of the 22nd annual international conference on Supercomputing – ICS '08. 978-1-60558-158-3. 309–318. https://escholarship.org/content/qt8js4v3f7/qt8js4v3f7.pdf?t=ptt3te.
22. CUDA Toolkit Documentation-->,CUDA C Programming Guide v8.0. nVidia Developer Zone . 22 March 2017. 19. January 2017.
23. Web site: NVCC forces c++ compilation of .cu files. 29 November 2011.
24. Web site: Precision & Performance: Floating Point and IEEE 754 Compliance for Nvidia GPUs . Nathan . Whitehead . Alex . Fit-Florea . November 18, 2014 . Nvidia.
25. Web site: CUDA-Enabled Products . CUDA Zone . Nvidia Corporation . 2008-11-03.
26. Web site: Coriander Project: Compile CUDA Codes To OpenCL, Run Everywhere. Phoronix.
27. Web site: cuda-on-cl. Perkins. Hugh. IWOCL. 2017. August 8, 2017.
28. Web site: hughperkins/coriander: Build NVIDIA® CUDA™ code for OpenCL™ 1.2 devices. GitHub. May 6, 2019.
29. Web site: CU2CL Documentation . chrec.cs.vt.edu.
30. Web site: GitHub – vosen/ZLUDA. .
31. Web site: GitHub – chip-spv/chipStar. .
32. Web site: PyCUDA.
33. Web site: pycublas. https://web.archive.org/web/20090420124748/http://kered.org/blog/2009-04-13/easy-python-numpy-cuda-cublas/. 2009-04-20. dead. 2017-08-08.
34. Web site: CuPy. en. 2020-01-08.
35. Web site: NVIDIA CUDA Programming Guide. Version 1.0. June 23, 2007.
36. Web site: NVIDIA CUDA Programming Guide. Version 2.1. December 8, 2008.
37. Web site: NVIDIA CUDA Programming Guide. Version 2.2. April 2, 2009.
38. Web site: NVIDIA CUDA Programming Guide. Version 2.2.1. May 26, 2009.
39. Web site: NVIDIA CUDA Programming Guide. Version 2.3.1. August 26, 2009.
40. Web site: NVIDIA CUDA Programming Guide. Version 3.0. February 20, 2010.
41. Web site: NVIDIA CUDA C Programming Guide. Version 3.1.1. July 21, 2010.
42. Web site: NVIDIA CUDA C Programming Guide. Version 3.2. November 9, 2010.
43. Web site: CUDA 11.0 Release Notes. NVIDIA Developer.
44. Web site: CUDA 11.1 Release Notes. NVIDIA Developer.
45. Web site: CUDA 11.5 Release Notes. NVIDIA Developer.
46. Web site: CUDA 11.8 Release Notes. NVIDIA Developer.
47. Web site: NVIDIA Quadro NVS 420 Specs. TechPowerUp GPU Database. 25 August 2023 .
48. Web site: NVIDIA Rolls Out Tegra X2 GPU Support In Nouveau. Larabel. Michael. Michael Larabel. Phoronix. March 29, 2017. August 8, 2017.
49. https://www.techpowerup.com/gpudb/3232/xavier Nvidia Xavier Specs
50. Web site: Welcome — Jetson LinuxDeveloper Guide 34.1 documentation .
51. Web site: NVIDIA Bringing up Open-Source Volta GPU Support for Their Xavier SoC .
52. Web site: NVIDIA Ada Lovelace Architecture .
53. https://developer.download.nvidia.com/video/gputechconf/gtc/2019/presentation/s9839-discovering-the-turing-t4-gpu-architecture-with-microbenchmarks.pdf Dissecting the Turing GPU Architecture through Microbenchmarking
54. Web site: H.1. Features and Technical Specifications Table 13. Feature Support per Compute Capability. docs.nvidia.com. en-us. 2020-09-23.
55. Web site: CUDA C++ Programming Guide .
56. Fused-Multiply-Add, actually executed, Dense Matrix
57. Web site: Technical brief. NVIDIA Jetson AGX Orin Series. nvidia.com. 5 September 2023.
58. Web site: NVIDIA Ampere GA102 GPU Architecture. nvidia.com. 5 September 2023.
59. Benchmarking and Dissecting the Nvidia Hopper GPU Architecture. 2402.13499v1 . Luo . Weile . Fan . Ruibo . Li . Zeyu . Du . Dayou . Wang . Qiang . Chu . Xiaowen . 2024 . cs.AR .
60. Web site: Datasheet NVIDIA A40. nvidia.com. 27 April 2024.
61. Web site: NVIDIA AMPERE GA102 GPU ARCHITECTURE . 27 April 2024 .
62. Web site: Datasheet NVIDIA L40 . 27 April 2024 .
63. In the Whitepapers the Tensor Core cube diagrams represent the Dot Product Unit Width into the height (4 FP16 for Volta and Turing, 8 FP16 for A100, 4 FP16 for GA102, 16 FP16 for GH100). The other two dimensions represent the number of Dot Product Units (4x4 = 16 for Volta and Turing, 8x4 = 32 for Ampere and Hopper). The resulting gray blocks are the FP16 FMA operations per cycle. Pascal without Tensor core is only shown for speed comparison as is Volta V100 with non-FP16 datatypes.
64. Web site: NVIDIA Turing Architecture Whitepaper. nvidia.com. 5 September 2023.
65. Web site: NVIDIA Tensor Core GPU. nvidia.com. 5 September 2023.
66. Web site: NVIDIA Hopper Architecture In-Depth . 22 March 2022 .
67. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
68. = product first 3 table rows
69. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
70. Sun . Wei . Li . Ang . Geng . Tong . Stuijk . Sander . Corporaal . Henk . Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numeric Behaviors . IEEE Transactions on Parallel and Distributed Systems. 34 . 1 . 2023. 10.1109/tpds.2022.3217824 . 246–261. 2206.02874 . 249431357 .
71. Web site: Parallel Thread Execution ISA Version 7.7 .
72. Raihan . Md Aamir . Goli . Negar . Aamodt . Tor . Modeling Deep Learning Accelerator Enabled GPUs . 2018 . cs.MS . 1811.08309 .
73. Web site: NVIDIA Ada Lovelace Architecture .
74. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
75. = product first 3 table rows
76. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
77. Dissecting the NVidia Turing T4 GPU via Microbenchmarking . 1903.07486 . Jia . Zhe . Maggioni . Marco . Smith . Jeffrey . Daniele Paolo Scarpazza . 2019 . cs.DC .
78. Book: https://ieeexplore.ieee.org/document/8875651 . RTX ON – The NVIDIA TURING GPU . 10.1109/HOTCHIPS.2019.8875651 . 2019 IEEE Hot Chips 31 Symposium (HCS) . 2019 . Burgess . John . 1–27 . 978-1-7281-2089-8 . 204822166 .
79. Dissecting the NVidia Turing T4 GPU via Microbenchmarking . 1903.07486 . Jia . Zhe . Maggioni . Marco . Smith . Jeffrey . Daniele Paolo Scarpazza . 2019 . cs.DC .
80. Book: https://ieeexplore.ieee.org/document/8875651 . RTX ON – The NVIDIA TURING GPU . 10.1109/HOTCHIPS.2019.8875651 . 2019 IEEE Hot Chips 31 Symposium (HCS) . 2019 . Burgess . John . 1–27 . 978-1-7281-2089-8 . 204822166 .
81. https://nvdam.widen.net/s/5bx55xfnxf/gtc22-whitepaper-hopper NVIDIA H100 Tensor Core GPU Architecture
82. https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#features-and-technical-specifications H.1. Features and Technical Specifications – Table 14. Technical Specifications per Compute Capability
83. https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth NVIDIA Hopper Architecture In-Depth
84. The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
85. Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
86. Web site: H.6.1. Architecture. docs.nvidia.com. en-us. 2019-05-13.
87. Web site: Demystifying GPU Microarchitecture through Microbenchmarking.
88. Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking. 1804.06826 . Jia . Zhe . Maggioni . Marco . Staiger . Benjamin . Scarpazza . Daniele P. . 2018 . cs.DC .
89. Web site: Tegra X1. 9 January 2015 .
90. Note that Dissecting the NVidia Turing T4 GPU via Microbenchmarking. 1903.07486 . Jia . Zhe . Maggioni . Marco . Smith . Jeffrey . Daniele Paolo Scarpazza . 2019 . cs.DC . disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
91. Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking. 1804.06826 . Jia . Zhe . Maggioni . Marco . Staiger . Benjamin . Scarpazza . Daniele P. . 2018 . cs.DC .
92. Web site: I.7. Compute Capability 8.x. docs.nvidia.com. en-us. 2022-10-12.
93. Web site: Appendix F. Features and Technical Specifications .  , page 148 of 175 (Version 5.0 October 2012).
94. Web site: nVidia CUDA Bioinformatics: BarraCUDA. 2019-07-19. BioCentric. en. 2019-10-15.
95. Web site: Part V: Physics Simulation. 2020-09-11. NVIDIA Developer. en.
96. Web site: oneAPI Programming Model . 2024-07-27 . oneAPI.io . en-US.
97. Web site: Specifications oneAPI . 2024-07-27 . oneAPI.io . en-US.
98. Web site: oneAPI Specification — oneAPI Specification 1.3-rev-1 documentation . 2024-07-27 . oneapi-spec.uxlfoundation.org.
99. Web site: Exclusive: Behind the plot to break Nvidia's grip on AI by targeting software . . 2024-04-05.
100. Web site: Question: What does ROCm stand for? · Issue #1628 · RadeonOpenCompute/ROCm. Github.com. January 18, 2022.