This page is a comparison of electronic design automation (EDA) software which is used today to design the near totality of electronic devices. Modern electronic devices are too complex to be designed without the help of a computer. Electronic devices may consist of integrated circuits (ICs), printed circuit boards (PCBs), field-programmable gate arrays (FPGAs) or a combination of them. Integrated circuits may consist of a combination of digital and analog circuits. These circuits can contain a combination of transistors, resistors, capacitors or specialized components such as analog neural networks, antennas or fuses.
The design of each of these electronic devices generally proceeds from a high- to a low-level of abstraction. For FPGAs the low-level description consists of a binary file to be flashed into the gate array, while for an integrated circuit the low-level description consists of a layout file which describes the masks to be used for lithography inside a foundry.
Each design step requires specialized tools, and many of these tools can be used for designing multiple types of electronic circuits. For example, a program for high-level digital synthesis can usually be used both for IC digital design as well as for programming an FPGA. Similarly, a tool for schematic-capture and analog simulation can generally be used both for IC analog design and for PCB design.
In the case of integrated circuits (ICs) for example, a single chip may contain today more than 20 billion transistors (which is more than two transistors for every human on Earth) and, as a general rule, every single transistor in a chip must work as intended. Since a single VLSI mask set can cost up to 10-100 millions, trial and error approaches are not economically viable. To minimize the risk of any design mistakes, the design flow is heavily automatized. EDA software assists the designer in every step of the design process and every design step is accompanied by heavy test phases. Errors may be present in the high-level code already, such as for the Pentium FDIV floating-point unit bug, or it can be inserted all the way down to physical synthesis, such as a missing wire, or a timing violation.
The world of electronic design automation (EDA) software for integrated circuit (IC) design is dominated by the three vendors Synopsys, Cadence Design Systems and Siemens EDA (Formerly Mentor Graphics, acquired in 2017 by Siemens) which have a revenue respectively of 4,2 billion US$, 3 billion US$ and 1,3 billion US$.
These vendors offer software bundles which allow to cover the full spectrum of IC design, from HDL synthesis to physical synthesis and verification.
The development of EDA software is tightly connected with the development of technology nodes. The properties of a specific semiconductor foundry, such as the transistor models, the physical characteristics and the design rules, are usually encoded in file formats which are proprietary to one or more EDA vendors. This set of files constitutes the process design kit (PDK) and it is usually developed as a joint effort between the foundry and an EDA vendor. Foundries therefore usually release PDKs which are compatible only for one specific EDA bundle. The information contained inside PDKs is usually considered confidential. PDKs are therefore usually protected by non disclosure agreements (NDAs) and may be shipped in an incomplete or in an encrypted form to the designers.
| Application and developer | Platform | Latest release | Schematic? | Simulation? | PCB editing? | User Interface Language(s) | Imports | Exports | Scripting support | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Version | Date | ||||||||||||||||
| rowspan="4" | Advanced Design System by Keysight EEsof EDA | POSIX[1] | rowspan="4" | 2019[2] | rowspan="4" | 2018-11-15 | rowspan="4" | rowspan="4", full-wave electromagnetic simulation and netlist simulation | rowspan="4" | rowspan="4" | en | rowspan="4" | HSPICE, SPICE, Spectre netlists; Gerber, Excellon, ODB++, artwork; more | rowspan="4" | HSPICE, SPICE, Spectre netlists; Gerber, Excellon, ODB++, artwork; more | rowspan="4" | Python, Application Extension Language (proprietary; "AEL") |
| Windows | |||||||||||||||||
| SuSE | |||||||||||||||||
| RHEL | |||||||||||||||||
| CircuitLogix by Logic Design | Windows | 10 | 2019-01 | , netlist simulation (analog and digital) | en | SPICE, Gerber, DXF | SPICE, PDF, Gerber, DXF | ||||||||||
| LTspice by Analog Devices (free) | Windows, macOS, Wine | 24.0.9 | 2024-02-02 | , netlist simulation (analog) | en | netlist | netlist | ||||||||||
| rowspan="2" | Micro-Cap (free, end-of-life) | Windows | rowspan="2" | 12.2.0.5 | rowspan="2" | 2021-06-17 (end-of-life) | rowspan="2" | rowspan="2", netlist simulation (analog and digital) | rowspan="2" | rowspan="2" | en, jp | rowspan="2" | HSPICE, PSPICE, SPICE3, netlists, Images, IBIS, Touchstone | rowspan="2" | SPICE text file, netlist, BOM, Protel, Accel, OrCad, PADS netlists, Schematic and Analysis Plots Images, Numeric Output Text, Excel | rowspan="2" | |
| Wine | |||||||||||||||||
| Application and developer | Platform | Latest release | Schematic? | Simulation? | PCB editing? | User Interface Language(s) | Imports | Exports | Scripting support | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Version | Date | ||||||||||||||||
| rowspan="2" | Altium Designer (former Protel) by Altium | Windows | rowspan="2" | 23.3[3] | rowspan="2" | 2023-03-16 | rowspan="2" | rowspan="2" | rowspan="2" | rowspan="2" | Multilingual | rowspan="2" | OrCAD, Allegro, PADS Logic, PADS PCB, Expedition, DxDesigner, EAGLE, P-CAD, Gerber, STEP, Solidworks, IDF, more | rowspan="2" | 3D PDF, Gerber, Gerber X2, Excellon, ODB++, DXF, STEP, OrCAD, EAGLE, EDB, more | rowspan="2" | Delphi, JS, VB |
| Wine | |||||||||||||||||
| CADSTAR, Board Designer, and Visula by Zuken | Windows | 2022.0 | 2022-08-31 | , SI & PI | en | PADS, OrCAD, P-CAD, Protel, DXF, IDF | PDF, Gerber, Excellon, ODB++, DXF, IDF more | COM, macros | |||||||||
| rowspan="2" | CircuitMaker by Altium | Windows | rowspan="2" | 2 | rowspan="2" | 2021-07 | rowspan="2" | rowspan="2" | rowspan="2" | rowspan="2" | en | rowspan="2" | Importer Removed since Last Version (1.3) | rowspan="2" | Gerber, Excellon, DXF, STEP, PDF | rowspan="2" | None |
| Wine | |||||||||||||||||
| rowspan="4" | CR-5000 by Zuken | POSIX | rowspan="4" | 13 | rowspan="4" | 2011-05-17 | rowspan="4" | rowspan="4", SI & PI | rowspan="4" | rowspan="4" | en, jp | rowspan="4" | EDIF, DXF, IGES, IDF, BSDL, STEP, ACIS, Gerber, Excellon, more | rowspan="4" | PDF, Gerber, Excellon, ODB++ (must request[4]), DXF, STEP, IPC D-356, IPC-2581, EPS, ACIS | rowspan="4" | |
| Windows | |||||||||||||||||
| Unix | |||||||||||||||||
| Linux | |||||||||||||||||
| rowspan="4" | CR-8000 by Zuken | POSIX | rowspan="4" | 2020 | rowspan="4" | 2020-06-30 | rowspan="4" | rowspan="4", SI & PI, IBIS-AMI/SERDES | rowspan="4" | rowspan="4" | en, jp | rowspan="4" | EDIF, DXF, IGES, IDF, BSDL, STEP, ACIS, Gerber, Excellon, more | rowspan="4" | PDF, Gerber, Excellon, ODB++ (must request), DXF, STEP, IPC D-356, IPC-2581, EPS, ACIS | rowspan="4" | |
| Windows | |||||||||||||||||
| Unix | |||||||||||||||||
| Linux | |||||||||||||||||
| DesignSpark PCB by RS Components | Windows | 9.0.3 | 2020-07-08 | , Spice | en | EAGLE, DXF, EDIF | Gerber, Excellon, ODB++, DXF, IDF, PDF, LPKF | ||||||||||
| rowspan="4" | DipTrace by Novarm | POSIX | rowspan="4" | 4.3.0.4 | rowspan="4" | 2023-01-18 | rowspan="4" | rowspan="4" (Spice netlist export) | rowspan="4" | rowspan="4" | 21 languages | rowspan="4" | Altium, Eagle, KiCad, OrCAD, P-CAD, PADS, Gerber, N/C Drill, DXF, BSDL Pinlist, Netlists | rowspan="4" | Gerber, Gerber X2, Excellon, ODB++, DXF, Eagle, P-CAD, PADS, OrCAD, IPC-D-356, STEP, VRML, Pick and Place, CSV, BOM | rowspan="4" | |
| Windows | |||||||||||||||||
| Mac | |||||||||||||||||
| Wine | |||||||||||||||||
| rowspan="4" | EAGLE by Autodesk/CadSoft Computer | POSIX | rowspan="4" | 9.6.2 | rowspan="4" | 2020-05-27 | rowspan="4" | rowspan="4" | rowspan="4" | rowspan="4" | de, en, zh, hu, ru | rowspan="4" | EAGLE (XML), ACCEL (P-CAD, Altium, Protel), ULTIBOARD, Netlists, BMP, Custom | rowspan="4" | EAGLE (XML), Protel, Netlists, Images, Gerber, Gerber X2, Excellon, Sieb & Meyer, HPGL, PostScript/EPS, PDF, Images, HyperLynx, IDF, Custom | rowspan="4" | Proprietary User Language Programming (ULP) |
| Windows | |||||||||||||||||
| Linux | |||||||||||||||||
| Mac | |||||||||||||||||
| rowspan="5" | EasyEDA | POSIX | rowspan="5" | 6.4.5 | rowspan="5" | 2020-08-19 | rowspan="5" | rowspan="5" | rowspan="5" | rowspan="5" | en, fr, de, pl, jp, ru, es, se, ua, zh ... | rowspan="5" | Altium, EAGLE, KiCad libraries, LTspice .asc/.asy files, JSON, Spice | rowspan="5" | PDF, PNG, SVG, JSON, Gerber, Excellon, Pick and Place CSV file, CSV-formatted drill chart, Bill of Materials CSV file, Altium netlist, FreePCB netlist, PADS Layout Netlist, Spice netlist. | rowspan="5" | JSON |
| Windows | |||||||||||||||||
| Linux | |||||||||||||||||
| Mac | |||||||||||||||||
| ChromeOS as a Web application | |||||||||||||||||
| rowspan="2" | NI Ultiboard and Multisim by National Instruments | Windows | rowspan="2" | 14.2 [5] | rowspan="2" | 2019-05-19 | rowspan="2" | rowspan="2" | rowspan="2" | rowspan="2" | en | rowspan="2" | MS*, MP*, EWB, Spice, OrCAD, UltiCap, Protel, Gerber, DXF, Ultiboard 4&5, Calay | rowspan="2" | BOM, Gerber, Excellon, IGES (3D), DXF (2D & 3D), SVG | rowspan="2" | |
| Web application[6] | |||||||||||||||||
| OrCAD | Windows | 17.4 - 22.1 | 2022-10-20 | en | EAGLE, PADS, Altium, STEP, DXF, IDF, IDX, OrCAD SDT, OrCAD Layout,OrCAD | PDF, Gerber, Gerber X2, Excellon drill/route, netlist, ODB++, DXF, IDF, IDX, STEP,3D PDF, IPC2581 | Tcl/TK, SKILL (Lisp) | ||||||||||
| Proteus by Labcenter Electronics Ltd | Windows | 8.17 | 2023-12-11 | en | Gerber, BMP, DXF | PDF, Gerber, GerberX2, Excellon, ODB++, DXF, IDF, PKP, testpoint file, metafile, BMP. | internal script | ||||||||||
| rowspan="2" | Pulsonix by WestDev Ltd | Windows | rowspan="2" | 12.5 | rowspan="2" | 2023 | rowspan="2" | rowspan="2" | rowspan="2" | rowspan="2" | en | rowspan="2" | Allegro, Altium, CadStar, EAGLE, OrCAD, PADS, P-CAD, Protel, Gerber, STEP, DXF, IDF, more | rowspan="2" | Gerber, Gerber X2, Excellon, ODB++, IPC-2581, PDF, DXF, STEP, IDF, BOM, more | rowspan="2" | Proprietary language, ActiveX |
| Wine | |||||||||||||||||
| rowspan="2" | TARGET 3001! | Windows | rowspan="2" | 30.2.0.63 | rowspan="2" | 2020-12-14 | rowspan="2" | rowspan="2" | rowspan="2" | rowspan="2" | en, de, fr | rowspan="2" | EAGLE, DXF, Gerber, Gerber, Excellon, BMP, CXF, STEP 3D | rowspan="2" | Gerber, Gerber X2, Excellon, EAGLE, HPGL, G-Code (Milling), CXF, STEP 3D, Excel BOMs, Pick&Place, GenCAD, FABmaster, IPC D-356, Test points, Netlists, OBJ, POV-Ray, PDF | rowspan="2" | Package generator scripts, BOM scripts, printing and PDF generator scripts, 3D scripts |
| Wine | |||||||||||||||||
| rowspan="4" | TINA | Windows | rowspan="4" | 12.0 | rowspan="4" | 2019-12 | rowspan="4" | rowspan="4" | rowspan="4" | rowspan="4" | 23 languages (en, de, fr, es and 19 other languages) | rowspan="4" | VHDL, Verilog, Verilog-A, and Verilog-AMS | rowspan="4" | VHDL, Verilog, Verilog-A, and Verilog-AMS | rowspan="4" | |
| Linux | |||||||||||||||||
| MacOS | |||||||||||||||||
| Android | |||||||||||||||||
| rowspan="3" | Upverter | POSIX | rowspan="3" | N/A | rowspan="3" | 2019-05-10 | rowspan="3" | rowspan="3" | rowspan="3" | rowspan="3" | en | rowspan="3" | Altium, OrCad, PDF, OpenJSON, EAGLE | rowspan="3" | PDF, Gerber, Excellon, netlist, PADS Layout Netlist, Tempo Automation, Pick and Place CSV, High-Res PNG, STL, CSV-formatted drill chart, CSV-formatted list of all parts | rowspan="3" | |
| Windows | |||||||||||||||||
| Web application | |||||||||||||||||
| rowspan="3" | 123D Circuits by Autodesk | POSIX | rowspan="3" | N/A | rowspan="3" | rowspan="3", + breadboard | rowspan="3" | rowspan="3" | rowspan="3" | en | rowspan="3" | EAGLE | rowspan="3" | Gerber | rowspan="3" | ||
| Windows | |||||||||||||||||
| Web application | |||||||||||||||||
| Application and developer | Platform | Latest release | Schematic? | Simulation? | PCB editing? | User Interface Language(s) | Imports | Exports | Scripting support | ||||||||
| Version | Date | ||||||||||||||||
Free and open-source (FOSS) EDA software bundles are currently under fast development mainly thanks to the DARPA and Google's openROAD project. The OpenROAD project offers a complete stack of tools from high-level synthesis down to layout generation[7] The flow includes Yosys for logic synthesis, OpenLane for physical synthesis and targets the SkyWater 130nm PDK. The flow is currently utilized to submit design for free fabrication at Google.[8] [9]
High-level synthesis software can generally be used for the design of both application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Most high-level synthesis software is used to edit and verify code written in one of the mainstream hardware description languages (HDL) like VHDL or Verilog. Other tools instead operate at a higher level of abstraction and allow to synthesize HDL code starting from languages like Chisel or SpinalHDL. The higher abstraction of such languages enables formal verification of HDL code.[10] [11]
| Name | Architecture | License | Comment |
|---|---|---|---|
| GHDL | VHDL analyzer, compiler, and simulator.[12] | ||
| Icarus Verilog | Verilog simulator | ||
| Posix | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog into cycle accurate C++ or SystemC code following 2-state synthesis (zero delay) semantics. Benchmarks reported on its website suggest it is several times faster than commercial event driven simulators such as ModelSim, NC-Verilog and VCS, while not quite as fast as commercial cycle accurate modeling tools such as Carbon ModelStudio and ARC VTOC. | ||
This list does not include schematic editors or simulators since these can generally be used both for Integrated Circuits (ICs) and for Printed Circuit Board (PCB) as long as device models are available.
| Name | Architecture | License | Comment | |
|---|---|---|---|---|
| Yes | VLSI circuit design tool with connectivity at all levels. Can also be used for schematic entry and PCB design. | |||
| Linux | BSD license | No | A very-large-scale integration layout tool | |
| Name | Architecture | License | Comment |
|---|---|---|---|
| any (C++11) | Mixed-signal circuit simulator | ||
| KTechLab is a schematic capture and simulator. It is specifically geared toward mixed signal simulation of analog components and small digital processors. | |||
| SPICE + XSPICE + Cider | |||
| Oregano | Schematic capture + spice simulation | ||
| Quite Universal Circuit Simulator (QUCS) | Schematic capture + Verilog + VHDL + simulation. Qucs-S fork supports SPICE backends Ngspice, Xyce, & SpiceOpus. | ||
| Used to produce netlists and publish high-quality drawings. | |||
| Name | Architecture | License | Imports | Exports | Scripting support | Comment | ||
|---|---|---|---|---|---|---|---|---|
| atopile | Linux, Mac, Windows | MIT License | No | - | Gerber, BOM | Python | Code-based EDA tool that allows hardware engineers to design electronic circuits and PCBs using a programming-like environment. It integrates hardware design specifications directly into code, enabling intelligent design capture, version control, and continuous integration practices.[13] | |
| Yes | - | Gerber | No | A printed circuit board design program for Microsoft Windows. FreePCB allows for up to 16 copper layers, both metric and US customary units, and export of designs in Gerber format. Boards can be partially or fully autorouted with the FreeRouting[14] autorouter by using the FpcROUTE Specctra DSN design file translator. | ||||
| Yes | gEDA symbols, KiCad symbols, SVG | Gerber, DIY etching, BOM, SVG, PDF, EPS | No | Protoboard view, schematic view, PCB view, Code (firmware) view. Includes customizable design rule checker. Includes common shaped boards like Arduino and Raspberry Pi shields. Allows spline curve traces. Only two layers (top and bottom). Outputs gerbers. | ||||
| Yes | gschem netlists, image as background | Gerber, Excellon, SVG, PDF, EPS, PNG, GIF, JPEG, Specctra, XYRS | Guile (Scheme) | Schematic, simulation, PCB editor, gerber view | ||||
| FreeRouting | Altium, CadStar, EAGLE (XML), P-CAD, Fabmaster, TinyCAD net lists, OrCAD EDIF | PDF, Gerber, Gerber X2, Excellon, netlist, VRML2, STEP, IDFv3 | Python | Full package for schematic and board design, etc. Design rule checking. User-defined symbols and footprints. Gerber/drill file creation. Graphic interface. Active user community. | ||||
| Yes | gschem netlists, Protel Autotrax, KiCad (legacy & s-expr layouts), EAGLE (XML & v3,4,5 binary layouts), eeschema netlists, mentor netlists, TinyCad netlists, Calay netlist, FreePCB/easyEDA netlist, LT-Spice, MUCS, Mentor Graphics Hyperlynx, image (BMP, JPG, GIF, PNG), HPGL, BXL, Specctra (DSN), PADS | Gerber/drill, SVG, PDF, EPS, PNG, GIF, JPEG, Specctra (DSN), PADS, Protel Autotrax, KiCad (legacy & s-expr), DXF, FidocadJ, Mentor Graphics Hyperlynx, template configurable XYRS/BOM | Python, Lua, Perl, Tcl, AWK (multiple dialects), Lisp & Scheme (multiple dialects), JavaScript, Ruby, Pascal, BASIC | Circuit layout program with extended file format support, DRC, parametric footprints, query language, and GUI and command line operation for batch processing and automation |