Chisel (programming language) explained

Constructing Hardware in a Scala Embedded Language (Chisel)
Paradigms:	Multi-paradigm concurrent, functional, imperative, object-oriented
Family:	Scala
Developer:	University of California, Berkeley
Latest Release Version:	3.6.0
Typing:	Inferred, static, strong, structural
Scope:	Lexical (static)
Programming Language:	Scala
Platform:	Java virtual machine (JVM) JavaScript (Scala.js) LLVM (Scala Native) (experimental)
File Formats:	-->

Chisel (an acronym for Constructing Hardware in a Scala Embedded Language^[1]) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level.^{[2] [3]}

Chisel is based on Scala as a domain-specific language (DSL). Chisel inherits the object-oriented and functional programming aspects of Scala for describing digital hardware. Using Scala as a basis allows describing circuit generators. High quality, free access documentation exists in several languages.^[4]

Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation.

Code examples

A simple example describing an adder circuit and showing the organization of components in Module with input and output ports:

class Add extends Module

A 32-bit register with a reset value of 0:

val reg = RegInit(0.U(32.W))

A multiplexer is part of the Chisel library:

val result = Mux(sel, a, b)

Use

Although Chisel is not yet a mainstream hardware description language, it has been explored by several companies and institutions. The most prominent use of Chisel is an implementation of the RISC-V instruction set, the open-source Rocket chip.^[5] Chisel is mentioned by the Defense Advanced Research Projects Agency (DARPA) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs.^[6] Google has used Chisel to develop a Tensor Processing Unit for edge computing.^[7] Some developers prefer Chisel as it requires 5 times lesser code and is much faster to develop than Verilog.^[8]

Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation using a program named FIRRTL.^[9]

See also

• VHDL
• Verilog
• SystemC
• SystemVerilog

Notes and References

1. Bachrach . J. . Vo . H. . Richards . B. . Lee . Y. . Waterman . A. . Avižienis . R. . Wawrzynek . J. . Asanović . K. . June 2012 . Chisel: constructing hardware in a Scala embedded language . 10.1145/2228360.2228584 . Association for Computing Machinery (ACM) . Proceedings of the 49th Annual Design Automation Conference (DAC 2012) . 1216–25 . 978-1-4503-1199-1 . San Francisco, California, US .
2. Web site: Chisel . 2020-07-08 . people.eecs.berkeley.edu . . California, U.S. . 2021-10-16 . https://web.archive.org/web/20211016083643/https://people.eecs.berkeley.edu/~jrb/Projects/chisel/chisel.htm . dead .
3. Web site: Bachrach . Jonathan . Chisel: Accelerating Hardware Design . . RISC-V International . California, U.S..
4. Book: Schoeberl, Martin . August 30, 2019 . Digital Design with Chisel . Kindle Direct Publishing . en, zh, ja, vi . 2nd . 978-1689336031.
5. Web site: rocket-chip . Asanović . Krste . Krste Asanović . etal. GitHub . RISC-V International . 11 November 2016.
6. News: Moore. Samuel K.. 2018-07-16. DARPA Plans a Major Remake of U.S. Electronics. IEEE Spectrum. Institute of Electrical and Electronics Engineers (IEEE). 2020-06-10.
7. Derek Lockhart, Stephen Twigg, Ravi Narayanaswami, Jeremy Coriell, Uday Dasari, Richard Ho, Doug Hogberg, George Huang, Anand Kane, Chintan Kaur, Tao Liu, Adriana Maggiore, Kevin Townsend, Emre Tuncer . 2018-11-16 . Experiences Building Edge TPU with Chisel . 2020-06-10.
8. Web site: 2021-07-05 . XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 - CNX Software . 2022-03-26 . CNX Software - Embedded Systems News . en-US.
9. Web site: Chisel/FIRRTL Hardware Compiler Framework . 2022-09-08 .