| Bull Gamma 60 | |
| Developer: | Compagnie des Machines Bull |
| Type: | Large-scale mainframe computer |
| Generation: | 2 |
| Release Date: | 1960 |
| Units Sold: | 17 |
| Os: | GGZ, GGU |
| Power: | 200-400 kVA |
| Cpuspeed: | 100 kHz |
| Memory: | Central memory: 32 kwords (core memory). Up to four drum memory extensions (25 kwords each). |
| Storage: | Up to 48 magnetic tape readers |
| Input: | Magnetic tape, punched cards, paper tape, teletypes |
| Dimensions: | Typically 3000-4000 sq.ft |
| Predecessor: | Bull Gamma 3 |
| Successor: | GE-600 series |
| Cpu: | Transistorized, distributed and multi-threaded. Up to 25 Processing Units. 24-bit words with 1 to 4 words data types. |
| Baseprice: | 10M Francs (1960, about $18M USD in 2023) |
The Bull Gamma 60 was a large transistorized mainframe computer designed by Compagnie des Machines Bull. Initially announced in 1957, the first unit shipped in 1960. It holds the distinction of being the world's first multi-threaded computer, and the first to feature an architecture specially designed for parallelism.[1] [2]
The Gamma 60 spearheaded numerous groundbreaking technologies during the early 1960s, notably in multi-programming, utilizing tools that were still in their nascent stages. Upon its release, its architecture garnered significant attention among machine designers, becoming a subject of study alongside contemporary supercomputers and being cited as an example for progress in computer design.[3] [4]
Despite its innovations, the Gamma 60's large footprint (close to 4000 sq.ft), high cost, energy consumption, and complexity ultimately resulted in limited commercial success, with about only twenty units sold worldwide. Its main competitors included the IBM 7070, 7090, and 7030 "Stretch".[5] The last Gamma 60 remained in service until 1974.
The Gamma 60 marked Bull's entry into core memory, solid-state logic and magnetic tape capabilities.[6] Its architectural core was based on a large, high-speed central memory, with an arbitrator (known as the Program Distributor) responsible for distributing data and instructions to the various units within the computer. The processor was segmented into a central unit and a series of discrete, specialized processing units. This design allowed for the concurrent operation of up to five clusters, each containing five processing units.[7]
Each unit in the computer, whether a processing unit or a peripheral device, operated autonomously and would request data and instructions from the central unit when they became available. Data transmission to and from the processing units occurred through two independent buses—one for transmission and another for retrieval.
The processor operated in a 24-bit parallel configuration, with its primary data types employing one, two, or four words, also referred to as 'catenae', ranging from 24 to 96 bits in width. Simpler and slower external devices often employed an 8-bit parallel logic internally. These devices communicated with the central unit via bit-serial messages for instruction and data transfer requests. All messages were asynchronous, and the machine, through priority classes, was designed to accommodate very high device latencies if necessary, even from an ALU (Arithmetic Logic Unit).
The processor was divided into four kinds of processing elements:
Even though up to twenty-five of those specialized processing units could run simultaneously, only one central unit (functioning as a dispatcher) existed in the machine, which does not classify as an SMP (Symmetric Multiprocessing) architecture.
Given the distribution of processing units across separate cabinets, the choice of a slower clock speed of 100 kHz, half of what was originally envisioned, was aimed at mitigating the impact of propagation delays. Although this imposed a limitation on the performance of individual processing units, Bull's strategy was to counterbalance it by parallelism and the ability to easily add additional processing units. Interestingly, while the Gamma 60 logic was transistorized, the operating voltage of the germanium transistors was too low to counter the impedance of the great distances that could sometimes occur between some cabinets and peripherals. As a result, vacuum tubes had to be used in certain instances to drive the clock and some I/O signals.[8]
In modern terms, the Gamma 60 CPU would be described as a hardware time-sharing central processor for asynchronous parallel processes, using an explicit fork-join parallelism at the instruction level.
The Gamma 60 foreshadowed the architecture of superscalar processors, where the role of its central memory is now partly assumed by caches. Additionally, it shared similarities with EPIC architectures such as Intel Itanium, in that each instruction was its own thread, and the management of execution concurrency and memory access coherence was placed under the responsibility of the programmer.
Central memory was implemented with a stack of core memory with a basic memory cycle of 10 μs, making it the fastest component of the Gamma 60 (in comparison, a fixed point addition required 100 microseconds). Main memory addresses were coded on 15-bits, allowing the central memory to store 32,768 words, or 96 kB.
The memory map was continuous and shared by all units, except for the first 128 bytes which were unit specific and contained a set of local registers. Since central memory had, by far, the lowest latency of all components, it constituted the heart of the Gamma 60. Henceforth, the processing units didn't have working memory besides their registers, instead, the Program Distributor dispatched data and instructions to them by loading pointers to the central memory into their registers.
The 128 bytes memory of each processing unit was implemented using planar core memory and followed the following map:
One exception was the Program Distributor which had its own set of registers.
The peripherals of the Gamma 60 were categorized into four distinct classes based on their latency and performance characteristics.[9]
Class 0 included the fastest and most time-critical peripherals. The Program Distributor favored this class over any other to transfer instructions and data. It consisted of two devices: the Logical Unit (binary ALU) and the operator desk.
Class 1 included the Arithmetic Unit (BCD ALU), the General Comparator and the Transcoder (translation unit).
Class 2 included storage devices, notably:
The magnetic drums acted as large memories with a slower access time than Central Memory (10 milliseconds versus 10 microseconds). Up to four drums could be added to the Gamma 60, each with a capacity of 128 tracks of 200 words (150 kB each). Their memory was not mapped to the main memory namespace but was accessed as would a magnetic tape.
Up to ten specialized I/O processors named Uniselectors could each control up to twelve tape units. However, only 48 tapes units could be connected simultaneously.
Magnetic tapes had a recording density of 200 bits per inch and a 730m or 1100m length. The magnetic tape units used phase modulation rather than NRZ (non-return-from-zero), a technology that had been previously developed for the drum memory of the Gamma 3.
Class 3 included slower recording equipment such as:
Finally, class 4 included the slowest peripherals, such as teletypes and typewriters.
The sequencing mechanism employed by the Gamma 60 encompassed an orchestration of instruction fetching and distribution, execution control, memory access, and inter-process communication. The following sequence details a complete instruction execution cycle:
Programming the Gamma 60 was tedious, as adequate development tools for parallel programming did not exist in those times. High-level languages only appeared two years after the Gamma 60 introduction.
Two kinds of machine languages existed:
Recognizing the need for a high-level language, Bull began the development of a new language for the Gamma 60 called AP3. However, this initiative was eventually abandoned in favor of ALGOL, in which Bull got significantly invested starting in the late 1950s.[11] The ALGOL 60 compiler was eventually released in December 1962.
While Algol solved many complexity issues with programming the Gamma 60, it was ill suited to business applications. Additionally, COBOL did not exist when the Gamma 60 was designed, and was still in its early stages during the computer lifespan. Furthermore, the Gamma 60 used a fork-join model which COBOL had not been designed to accommodate. As a result, developers had no alternative but to use code B for programming the Gamma 60 in business applications.
This absence of advanced high-level tools for breaking down tasks into small concurrent threads meant that most programs only utilized a fraction of the hardware's capabilities.[12]
A complete Gamma 60 instruction was composed of a series of 24-bit words of four types:
A complete instruction must always last with a directive.
The instruction formats could vary depending on the processing unit, and supported direct, relative and indirect memory addressing. The Gamma 60 primarily performed memory operations through load-store operations in the main memory, or used processing instructions to manipulate registers in the processing units. Multiprocessing was achieved with two instructions: cut ("coupure") activated a processing unit by specifying a program address, while simu ("simultané") enabled an asynchronous branch for another unit.
As an example, considering the following expression:
a=b*c
d=a+d
An early operating system, GGZ (Gestion Générale Zéro, or General Management version Zero), was developed for the Gamma 60. It was delivered as a compact resident supervisor stored on magnetic tape, containing a bootloader, resource table, error handler and an operator command interpreter. The bootloader was capable of initializing several variables during boot or accept them from the operator.
A more advanced operating system, GGU (Gestion Générale des Unités), was later shipped but remained incomplete as the computer neared the end of its lifespan. GGU introduced features like memory management, enhanced error recovery, and automated job management and scheduling.[13] It was notably used at RTT in Belgium.
Unfortunately, the software tools available in the late fifties and early sixties, such as compilers, operating systems, and debuggers, were still too primitive to fully utilize the capabilities of the Gamma 60. Compilers allowing automatic exploitation of concurrency for an EPIC architecture only emerged in the late 1990s, after a development period that exceeded the entire lifespan of the Gamma 60.
Due to the significant challenges in program development with the crude tools of the times, Bull lost several clients to IBM, whose machines, while single-processor, were simpler and more cost-effective.[14]
About twenty large companies and organizations showed interest in the Gamma 60 in the late fifties and early sixties, although not all of them made a purchase. The unit shipped to AG Vie was the first one manufactured, but encountered reliability issues as some hardware problems were still being discovered and resolved. As the company's patience ran out, the computer was decommissioned prematurely. Gaz de France (now Engie) also expressed interest but later withdrew due to implementation and operational complexities. The contract was eventually awarded to the IBM 7070. Other clients are listed in the table below:
| Client | Country | Order year | Commissioning year | Decommissioning year | Successor | |
|---|---|---|---|---|---|---|
| AGVie |  France | 1957 | 1960 | 1962 | Gamma 30 | |
| EDF | France | 1957 | 1960 | 1964 | IBM 7090 | |
| CNEP(now BNP Paribas) | France | 1957 | 1961[15] | 1969 | GE 600 | |
| Union | France | 1957 | 1963 | 1969 | GE 600 | |
| SNCF | France | 1958 | 1960 | 1966 | ||
| RTT |  Belgium | 1958 | 1961 | 1974 | Siemens 4004 | |
| Urbaine Seine | France | 1959 | 1961 | 1970 | GE 600 | |
| GMF | France | 1959 | 1962 | 1973 | GE 615 | |
| Credito Italiano |  Italy | 1960 | 1961 | Unknown | ||
| CEA | France | 1960 | 1962 | 1964 | CDC 3600 | |
| Banca Lavoro | Italy | 1960 | 1962 | Unknown | ||
| Printemps | France | 1961 | 1962 | 1965 | ||
| HBNPC | France | 1961 | 1963 | 1970 | ||
| TLF | France | 1962 | 1964 | 1971 | ||
| Mitsubishi |  Japan | 1963 | 1965 | 1971 | GE 635 | |
| RTT B | Belgium | 1964 | 1966 | 1974 |
The Gamma 60 that remained in service the longest was also at RTT, where it operated continuously for 13 years. The decision to replace its two Gamma 60 systems in the mid-1970s with several Siemens 4004 computers was politically motivated, as the Belgian government had established a five-year contract linking their information systems to Siemens and Phillips.
Bull committed significant resources to the development of the Gamma 60, even though the practical utilization of its architectural innovations would not become feasible until the 1980s or even the 1990s, greatly impacting its commercial success. The challenges it faced in the market led to financial difficulties that hindered the creation of a more accessible, scaled-down version suitable for smaller companies. Instead, the mid-range Gamma 30 transitioned to a licensed version of the simpler and more traditional RCA 301 computer, which, while successful in competing with the IBM 1401, could not capitalize on the innovations of the Gamma 60.[18]
In 1963, Bull was eventually purchased by General Electric, and the primary successor to the Gamma 60 became the GE 600 family starting in 1965.
No surviving specimens of the Gamma 60 exist today, save for some of its components displayed in certain museums. The NAM Computer Museum in Namur, Belgium, showcases a detailed scaled model of the Gamma 60 as it appeared at RTT. The Gamma 60 was also featured in the Jean-Luc Godard film Alphaville (1965), portraying the antagonist Alpha 60 computer.[19]
No Gamma 60 emulator is known to exist .