Bluespec Explained
Bluespec, Inc. is an American semiconductor tool design company co-founded by Massachusetts Institute of Technology (MIT) professor Arvind in June 2003 and based in Framingham, Massachusetts. Arvind had formerly founded Sandburst in 2000, which specialized in producing chips for 10 Gigabit Ethernet (10GE) routers, for this task.[1] [2] Bluespec has two product lines which are primarily for application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) hardware designers and architects. Bluespec supplies high-level synthesis (electronic system-level (ESL) logic synthesis) with register-transfer level (RTL). The first Bluespec workshop was held on August 13, 2007, at MIT.[3]
Bluespec SystemVerilog
Bluespec
| Bluespec |
| Paradigm: | Functional |
| Family: | Verilog, Haskell |
| Developer: | Bluespec Inc. |
| Latest Release Version: | Version 2022.01 |
| Latest Release Date: | January 2022 |
| Scope: | HDL |
| File Ext: | .bsv |
| File Formats: | --> |
| Implementations: | Bluespec Compiler (BSC); Toy Bluespec Compiler |
| Dialects: | SystemVerilog (BSV), Haskell (BH: Bluespec Classic) |
Arvind had developed the Bluespec language named Bluespec SystemVerilog (BSV), a high-level functional programming hardware description programming language which was essentially Haskell extended to handle chip design and electronic design automation in general.[4] The main designer and implementor of Bluespec was Lennart Augustsson. Bluespec is partially evaluated (to convert the Haskell parts) and compiled to the term rewriting system (TRS). It comes with a SystemVerilog frontend.[5] BSV is compiled to the Verilog RTL design files.
Tools
BSV releases are shipped with the following hardware development kit:
- BSV compiler
The compiler takes BSV source code as input and generates a hardware description for either Verilog or Bluesim as output. It was opensourced by Bluespec inc. in 2020 under New BSD License terms.
- Libraries
BSV is shipped with a set programming idioms and hardware structures
- Verilog modules
Several primitive BSV elements, such as first in, first out (FIFOs) and processor registers, are expressed as Verilog primitives.
- Bluesim
A cycle simulator for BSV designs.
- Bluetcl
A collection of Tcl extensions, scripts, and packages to link into a Bluespec design.References
- Book: Hudak . Paul (Yale University) . Paul Hudak . Hughes . John (Chalmers University) . John Hughes (computer scientist) . Peyton Jones . Simon (Microsoft Research) . Simon Peyton Jones . Wadler . Philip Wadler (University of Edinburgh) . Philip Wadler . June 9–10, 2007 . A history of Haskell: being lazy with class . HOPL III: Proceedings of the third ACM SIGPLAN conference on History of programming languages . Association for Computing Machinery . San Diego, California . 12-1–12-55 . 10.1145/1238844.1238856 . [it] is basically Haskell with some extra syntactic constructs for the term rewriting system (TRS) that describes what the hardware does. The type system has been extended with types of numeric kind..
- Peyton Jones . Simon . Simon Peyton Jones . June 2007 . A History of Haskell: being lazy with class . Microsoft Research.
External links
Notes and References
- Web site: Arvind elected as India National Academy of Sciences Foreign Fellow . 2014-12-23 . MIT News.
- Web site: Maffei . Lucia . 2023-02-09 . Form D Friday: Lexington blood tech startup raises $13.2M . American City Business Journals.
- Web site: The First Bluespec Workshop . 2019-05-04 . csg.csail.mit.edu.
- "[it] is basically Haskell with some extra syntactic constructs for the term rewriting system (TRS) that describes what the hardware does. The type system has been extended with types of numeric kind." pg 43 of Hudak, Jones, et al. 2007
- Hudak, Jones, et al. 2007
