POKEY, an acronym for Pot Keyboard Integrated Circuit,[1] is a digital I/O chip designed by Doug Neubauer at Atari, Inc.[2] for the Atari 8-bit computers. It was first released with the Atari 400 and Atari 800 in 1979 and is included in all later models and the Atari 5200 console. POKEY combines functions for reading paddle controllers (potentiometers) and computer keyboards as well as sound generation and a source for pseudorandom numbers. It produces four voices of distinctive square wave audio, either as clear tones or modified with distortion settings.[3] Neubauer also developed the Atari 8-bit killer application Star Raiders which makes use of POKEY features.
POKEY chips are used for audio in many arcade video games of the 1980s including Centipede, Missile Command, Asteroids Deluxe, and Gauntlet. Some of Atari's arcade systems use multi-core versions with 2 or 4 POKEYs in a single package for more audio channels. The Atari 7800 console allows a game cartridge to contain a POKEY, providing better sound than the system's audio chip. Only two licensed games make use of this: the ports of Ballblazer and Commando.
The LSI chip has 40 pins and is identified as C012294.[4] The USPTO granted U.S. Patent 4,314,236 to Atari on February 2, 1982 for an "Apparatus for producing a plurality of audio sound effects".[5] The inventors listed are Steven T. Mayer and Ronald E. Milner.
By part number:
Atari used several different manufacturers for the chip, however AMI produced most of them in 1983 onward. Early chips were manufactured on a 5 micrometer process, this was later shrunk to 3 micrometers. AMI-produced POKEYs have been reported as having a high failure rate compared with other brands of the chip; the reasons for this are unclear, but speculated to be a fault of the chip packaging or bonding wires. Some limited success in reviving nonfunctional POKEYs by heating them in an oven has been reported. There also exist modern FPGA replacements such as POKEYOne.[7]
| Pin Name | Pin Number(s) | Description | |
|---|---|---|---|
| A0 - A3 | 36, 35, 34, 33 | Memory Address Input | |
| ACLK | 27 | Serial Clock Output | |
| AUD | 37 | Audio Output | |
| BCLK | 26 | Bi-direction Clock I/O | |
| CS0 | 30 | Chip Select | |
| CS1 | 31 | Chip Select | |
| D0 - D7 | 38, 39, 40, 2, 3, 4, 5, 6 | Data Bus I/O | |
| IRQ | 29 | Interrupt Request Output | |
| K0 - K5 | 23, 22, 21, 20, 19, 18 | Keyboard Scan Output | |
| KR1 - KR2 | 25, 16 | Keyboard Row strobe Input | |
| P0 - P7 | 14, 15, 12, 13, 10, 11, 8, 9 | Potentiometer (Paddle) Scan | |
| R/W | 32 | Read/Write I/O Control | |
| SID | 24 | Serial Input Data | |
| SOD | 28 | Serial Output Data | |
| Vcc | 17 | Power +5 Volts | |
| Vss | 1 | Ground | |
| Ø2 | 7 | Phase 2 Clock Input |
The Atari 8-bit computers map POKEY to the $D2xxhex page and the Atari 5200 console maps it to the $E8xxhex page.
POKEY provides 29 Read/Write registers controlling Sound, Paddle input, keyboard input, serial input/output, and interrupts. Many POKEY register addresses have dual purposes performing different functions as a Read vs a Write register. Therefore, no code should read Hardware registers expecting to retrieve the previously written value.
This problem is solved for some registers by Operating System "Shadow" registers implemented in regular RAM that mirror the values of hardware registers. During the Vertical Blank the Operating System copies the Shadow registers in RAM for Write registers to the corresponding hardware register, and updates Shadow values for Read registers from the hardware accordingly. Therefore, writes to hardware registers which have corresponding shadow registers will be overwritten by the value of the Shadow registers during the next vertical blank.
Reading values directly from hardware at an unknown stage in the display cycle may return inconsistent results (an example: reading potentiometers). Operating System Shadow registers for Read registers would usually be the preferred source of information.
Some Write hardware registers do not have corresponding Shadow registers. They can be safely written by an application without the value being overwritten during the vertical blank. If the application needs to know the last value written to the register then it is the responsibility of the application to implement its own shadow value to remember what it wrote.
| Name | Description | Read/Write | Hex Addr | Dec Addr | Shadow Name | Shadow Hex Addr | Shadow Dec Addr | |
|---|---|---|---|---|---|---|---|---|
| Audio Channel 1 Frequency | Write | $D200 | 53760 | |||||
| Potentiometer (Paddle) 0 | Read | $D200 | 53760 | PADDL0 | $0270 | 624 | ||
| Audio Channel 1 Control | Write | $D201 | 53761 | |||||
| Potentiometer (Paddle) 1 | Read | $D201 | 53761 | PADDL1 | $0271 | 625 | ||
| Audio Channel 2 Frequency | Write | $D202 | 53762 | |||||
| Potentiometer (Paddle) 2 | Read | $D202 | 53762 | PADDL2 | $0272 | 626 | ||
| Audio Channel 2 Control | Write | $D203 | 53763 | |||||
| Potentiometer (Paddle) 3 | Read | $D203 | 53763 | PADDL3 | $0273 | 627 | ||
| Audio Channel 3 Frequency | Write | $D204 | 53764 | |||||
| Potentiometer (Paddle) 4 | Read | $D204 | 53764 | PADDL4 | $0274 | 628 | ||
| Audio Channel 3 Control | Write | $D205 | 53765 | |||||
| Potentiometer (Paddle) 5 | Read | $D205 | 53765 | PADDL5 | $0275 | 629 | ||
| Audio Channel 4 Frequency | Write | $D206 | 53766 | |||||
| Potentiometer (Paddle) 6 | Read | $D206 | 53766 | PADDL6 | $0276 | 630 | ||
| Audio Channel 4 Control | Write | $D207 | 53767 | |||||
| Potentiometer (Paddle) 7 | Read | $D207 | 53767 | PADDL7 | $0277 | 631 | ||
| Audio Control | Write | $D208 | 53768 | |||||
| Read 8 Line POT Port State | Read | $D208 | 53768 | |||||
| Start Timers | Write | $D209 | 53769 | |||||
| Keyboard Code | Read | $D209 | 53769 | CH | $02FC | 764 | ||
| Reset Serial Status (SKSTAT) | Write | $D20A | 53770 | |||||
| Random Number Generator | Read | $D20A | 53770 | |||||
| Start POT Scan Sequence | Write | $D20B | 53771 | |||||
| Serial Port Data Output | Write | $D20D | 53773 | |||||
| Serial Port Data Input | Read | $D20D | 53773 | |||||
| Interrupt Request Enable | Write | $D20E | 53774 | POKMSK | $10 | 16 | ||
| IRQ Status | Read | $D20E | 53774 | |||||
| Serial Port Control | Write | $D20F | 53775 | SSKCTL | $0232 | 562 | ||
| Serial Port Status | Read | $D20F | 53775 |
In the individual register listings below the following legend applies:
| Bit Value | Description | |
|---|---|---|
| 0 | Bit must be 0 | |
| 1 | Bit must be 1 | |
| ? | Bit may be either 0 or 1, and is used for a purpose. | |
| - | Bit is unused, or should not be expected to be a certain value | |
| label | Refer to a later explanation for the purpose of the bit. |
Pokey contains a programmable sound generator; four audio channels with separate frequency, noise and voice level controls.
Each channel has an 8-bit frequency divider and an 8-bit register to select noise and volume.
POKEY's sound is distinctive: when the four channels are used independently, there is noticeable detuning of parts of the 12-tone equal temperament scale, due to lack of pitch accuracy. Channels may be paired for higher accuracy; in addition, multiple forms of distortion are available, allowing a thicker sound. The distortion is primarily used in music for bass parts.
One of the sound-engines developed for the Atari 8-bit family was called the AMP engine (Advanced Music Processor). This was used by the musician Gary Gilbertson.
The AUDF* registers control the frequency or pitch of the corresponding sound channels. The AUDF* values also control the POKEY hardware timers useful for code that must run in precise intervals more frequent than the vertical blank.
Each AUDF* register is an 8-bit value providing a countdown timer or divisor for the pulses from the POKEY clock. So, smaller values permit more frequent output of pulses from POKEY, and larger values, less frequent. The values $0hex/0dec to $FFhex/255dec are incremented by POKEY to range from $1hex/1dec to $100hex/256dec. The actual audible sound pitch is dependent on the POKEY clock frequency and distortion values chosen. See Audio Channel Control and Audio Control.
Audio Channel 1 Frequency
Audio Channel 2 Frequency
Audio Channel 3 Frequency
Audio Channel 4 Frequency
The Audio Channel control registers provide volume and distortion control over individual sound channels. Audio may also be generated independently of the POKEY clock by direct volume manipulation of a sound channel which is useful for playing back digital samples.
Audio Channel 1 Control
Audio Channel 2 Control
Audio Channel 3 Control
Audio Channel 4 Control
Bit 0-3: Control over volume level, from 0 to F.
Bit 4: Forced volume-only output. When this bit is set the channel ignores the AUDF timer, noise/distortion controls, and high-pass filter. Sound is produced only by setting volume bits 0:3 . This feature was used to create digital audio via pulse-code modulation.
Bit 5-7: Shift register settings for noises/distortion. Bit values described below:
| Noise Value | Bits Value | Description | |
|---|---|---|---|
| 0 0 0 | $00 | 5-bit then 17-bit polynomials | |
| 0 0 1 | $20 | 5-bit poly only | |
| 0 1 0 | $40 | 5-bit then 4-bit polys | |
| 0 1 1 | $60 | 5-bit poly only | |
| 1 0 0 | $80 | 17-bit poly only | |
| 1 0 1 | $A0 | no poly (pure tone) | |
| 1 1 0 | $C0 | 4-bit poly only | |
| 1 1 1 | $E0 | no poly (pure tone) |
Generating random noises is served by reading 8 bits from top of 17-bit shift register. That registers are driven by frequency 1.79 MHz for NTSC or 1.77 MHz for PAL. Its outputs can by used independently by each audio channels' divider rate.
Audio Control allows the choice of clock input used for the audio channels, control over the high-pass filter feature, merging two channels together allowing 16-bit frequency accuracy, selecting a high frequency clock for specific channels, and control over the "randomness" of the polynomial input.
"1" means "on", if not described:
All frequency dividers (AUDF) can be driven at the same time by 64 kHz or 15 kHz rate.
Frequency dividers 1 and 3 can be alternately driven by CPU clock (1.79 MHz NTSC, 1.77 MHz PAL).Frequency dividers 2 and 4 can be alternately driven by output of dividers 1 and 3.In this way, POKEY makes possible connecting of 8-bit channels to create sound with 16-bit accuracy.
Possible channel configurations:
POKEY has eight analog to digital converter ports most commonly used for potentiometers, also known as Paddle Controllers. The analog inputs are also used for the Touch Tablet controller, and the 12-button, video game Keyboard Controllers. Each input has a drop transistor, which can be set on or off from software. The timers can also be used to support a light pen, by connecting a photodiode to the drop transistor, which captures the timer when the electron beam in the television passes by the pen. The vertical position of the pen had to be read separately.
SHADOW: PADDL0 $0270
Paddle Controller 0 Input
SHADOW: PADDL1 $0271
Paddle Controller 1 Input
SHADOW: PADDL2 $0272
Paddle Controller 2 Input
SHADOW: PADDL3 $0273
Paddle Controller 3 Input
SHADOW: PADDL4 $02704
Paddle Controller 4 Input
SHADOW: PADDL5 $0275
Paddle Controller 5 Input
SHADOW: PADDL6 $0276
Paddle Controller 6 Input
SHADOW: PADDL7 $0277
Paddle Controller 7 Input
Each input has 8-bit timer, counting time when each TV line is being displayed. This had the added advantage of allowing the value read out to be fed directly into screen coordinates of objects being driven by the paddles. The Atari Paddle values range from 0 to 228, though the maximum possible is 244. The Paddle controller reads 0 when turned to its maximum clockwise position, and returns increasing values as it is turned counter-clockwise ending at its maximum value.
The Paddle reading process begins by writing to POTGO which resets the POT* values to 0, the ALLPOT value to $FF, and discharges the potentiometer read capacitors. The POT* values increment as they are being scanned until reaching the resistance value of the potentiometer. When the Paddle reading is complete the corresponding bit in ALLPOT is reset to 0.
The Paddle scanning process can take the majority of a video frame to complete. The Atari Operating System takes care of Paddle reading automatically. The Paddles are read and paddle scanning initiated during the stage 2 vertical blank. Paddle values are copied to shadow registers. (Note that Paddle triggers are actually joystick direction input read from PIA.)
A faster mode of scanning the Paddles is possible by setting a bit in SKCTL. The reading sequence completes in only a couple scan lines, but the value is less accurate.
Potentiometer Scanning Status
Each bit corresponds to one potentiometer input (the POT* registers). When paddle scanning is started by writing to POTGO each paddle's bit in ALLPOT is set to 1. When a paddle's scan is complete the corresponding bit in ALLPOT is reset to 0 indicating the value in the associated POT* register is now valid to read.
Start Potentiometer Scan
Writing to POTGO initiates the potentiometer (Paddle) scanning process. This resets the POT* values to 0, the ALLPOT value to $FF, and discharges the potentiometer read capacitors. As each potentiometer scan completes the bit corresponding to the potentiometer in ALLPOT is cleared indicating the value of the associated POT* register is valid for reading.
Contains:
POKEY is a sort of UART. Usually one of the doubled audio channels is used as baud rate generator. The standard baud rate is 19.2 kbit/s, the maximum possible baud rate is 127 kbit/s. A byte put into the SEROUT register is automatically sent over the serial bus. The data frame contains 10 bits: 1 start bit, 8 data bits, 1 stop bit. The voltage levels are 0 V (logical 0) and +4 V (logical 1). It is possible to connect the Atari serial port with an RS-232 port by means of a simple voltage converter.
Each input/output operation causes POKEY's internal shift registers to change value, so when programming for POKEY, it is necessary to re-initialise some values after each operation is carried out.
Reset Serial Port Status (SKSTAT).
A write to this register will reset bits 5 through 7 of SKSTAT which are latches to 1. The latches flag keyboard overrun, Serial data input overrun, and Serial data input frame error.
Serial port data output byte.
This is a parallel "holding" register for the eight bit (one byte) value that will be transferred to the serial shift register for output one bit at a time. When the port is ready to accept data for output a Serial Data Out interrupt informs the Operating System that it can write a byte to this output register.
Serial port data input byte.
Like SEROUT, also a parallel "holding" register. This holds the eight bit (one byte) value assembled by the serial shift register reading the data input one bit at a time. When a full byte is read a Serial Data In interrupt occurs informing the Operating System that it can read the byte from this register.
Serial Port Control
Bit 0: Enable "debounce" scanning which is intended to eliminate noise or jitter from mechanical switches. A value of 1 enables POKEY to use an internal comparison register while scanning keys. A key must be detected in two simultaneous scans before it is identified as pressed, and it must be seen released for two consecutive scans to be considered released. This should be enabled to maintain normal keyboard handling with the Operating System.
Bit 1: Set to 1 to enable keyboard scanning. This should be enabled to maintain normal keyboard handling with the Operating System.
Bit 2: Set to 1 to enable fast, though less accurate Potentiometer scanning. Fast Pot scanning increments the counter on every cycle and returns a usable result within two scan lines. The Operating System uses the slow Pot Scanning which increments the counter once every 114 cycles (scan line) taking a frame (1/60th second) to produce a result. The OS reads the Pot values during its Vertical Blank Interrupt (VBI) and copies the result to the potentiometer Shadow registers in RAM. It then resets POTGO for the next read during the next VBI.
Bit 3: Enable Serial port two-tone mode. When enabled, 1 and 0 bits output to the SIO bus are replaced by tones set by timers 1 and 2. This is ordinarily used for writing analog tones representing digital data to cassette tape.
Bit 4-6: Clock Timing Control for serial port operation. Bit values described below:
| Port Control [6:4] | Bits Value | Input Clock | Output Clock | Bidirectional Clock | |
|---|---|---|---|---|---|
| 0 0 0 | $00 | External | External | Input | |
| 0 0 1 | $10 | Channels 3+4 (async) | External | Input | |
| 0 1 0 | $20 | Channel 4 | Channel 4 | Output Channel 4 | |
| 0 1 1 | $30 | Channel 3+4 (async) | Channel 4 (async) | Input | |
| 1 0 0 | $40 | External | Channel 4 | Input | |
| 1 0 1 | $50 | Channel 3+4 (async) | Channel 4 (async) | Input | |
| 1 1 0 | $60 | Channel 4 | Channel 2 | Output Channel 4 | |
| 1 1 1 | $70 | Channel 3+4 (async) | Channel 2 | Input |
Bit 7: Forces a known 0 output, so that timer 2 can reset timer 1 in two-tone serial output mode.
Serial Port Status
SHADOW: CH $02FC
Keyboard Code
Six key register of actually pushed keys (K0 K5), which contains values from 00 to 3F. Contains 2 control values. One of them acts as decoder of all 6 values. Second control values is used to decode special key values — CTRL, SHIFT and BREAK.