| Altos Design Automation | |
| Fate: | Acquired (May 10, 2011) |
| Successor: | Cadence Design Systems |
| Type: | Private |
| Location: | San Jose, California, United States |
| Key People: | Jim McCanny, CEO and Co-founderKen Tseng, CTO and Co-founder Kevin Chou, VP R&D and Co-founder Wenkung Chu, R&D Architech and Co-founder |
Altos Design Automation, Inc. was an electronic design automationsoftware company. Altos developed and marketed cell and semiconductorintellectual property (IP) characterization tools that created library viewsfor timing, signal integrity and power analysis and optimization.[1] [2] The Altostools were fully automated and the company claimed that its tools areextremely fast. The Altos tools were used by engineers employing bothcorner-based and statistical-based design implementation flows to reducetime-to -market and improve yield.[3] [4]
Altos was founded in January 2005 in Santa Clara,California by former employees of Cadence Design Systems. All members of theteam worked at CadMOS where they were responsible for the development ofSignal Integrity analysis tools for both cell- and transistor-level digitalIC designers. In May 2011 Altos was acquired by Cadence.[5]
Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates statistical static timing analysis (SSTA) models for a number of commercial SSTA products from a single characterization run.
Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems.