Alternate Instruction Set Explained

The Alternate Instruction Set (AIS) is a second 32-bit instruction set architecture found in some x86 CPUs made by VIA Technologies. On these VIA C3 processors, the second hidden processor mode is accessed by executing the x86 instruction JMPAI . If AIS mode has been enabled, the processor will perform a JMP EAX and begin executing AIS instructions at the address of the EAX register. Using AIS allows native access to the Centaur Technology-designed RISC core inside the processor.^[1]

Instruction format

Register mapping between AIS and x86! AIS number! x86 name

R0	EAX
R1	ECX
R2	EDX
R3	EBX
R4	ESP
R5	EBP
R6	ESI
R7	EDI
R8‒R15	…

The manufacturer describes the Alternate Instruction Set as "an extended set of integer, MMX, floating-point, and 3DNow! instructions along with additional registers and some more powerful instruction forms".^[2] Every AIS instruction is prefixed with the 3-byte sequence 0x8D8400 followed by the 32-bit instruction; this prefix form for the AIS instructions makes them appear to be x86 Load Effective Address (LEA) instructions.In 2018 researcher Christopher Domas reported that the prefix 0x620405 (x86 BOUND) also worked.

A proposal made in 2002 to add AIS support to the Netwide Assembler (NASM) was partially declined in 2005, on the basis that NASM was an x86 assembler, and AIS is a separate instruction set.^[3] An assembler is available from Domas's 2018 research.

In 2007 a patent named some microcode instructions as load and store to/from main RAM, and loadPRAM and storePRAM to/from private-RAM inside the processor.^[4] The Centaur Technologies verification team, in a 2014 paper about the VIA Nano, included some short lists of micro-instructions including ADDIG, JLINK, JMP_ALL, MVIG, NLOOPE, STORE_PRAM, plus micro-operations XADD and XSUB. Micro-operations were shown to have a format that includes the fields opcode, exec unit, src width, src1, src2, dest width, dest, write flags? and end routine?.^[5]

A 2002 programming reference for the Alternate Instruction set^[6] and an accompanying appnote^[7] were added to the Bitsavers archive in May 2021.

Availability

From x86 mode, the availability of the Alternate Instruction Set can be detected by executing a CPUID with the EAX register set to 0xc0000001 and then examining the EDX register. If EDX is set to 1, then AIS is supported. If EDX is also set to 1, then AIS is enabled.^[8] If AIS is supported by the CPU, then its status can be checked and altered through the Model-specific registers, by checking and setting the Feature Control Register (FCR, register 0x1107). If ("ALTINST") is set to 1, then AIS is enabled.^[8]

The Microsoft Windows NT kernel KiGetFeatureBits initialisation function proactively disables Alternate Instruction mode on boot up.^[9] If the x86 JMPAI jump instruction is executed when AIS mode is disabled, then the processor will generate an Invalid Instruction exception.Setting the AIS-enabled bit requires privileged access, and should be set using a read-modify-write sequence.^[10]

Privilege elevation

In 2018 Christopher Domas discovered that some Samuel 2 processors came with the Alternate Instruction Set enabled by default and that by executing AIS instructions from user space, it was possible to gain privilege escalation from Ring 3 to Ring 0.^[11] Domas had partially reverse engineered the AIS instruction set using automated fuzzing against a cluster of seven thin clients.^[12] Domas used the terms "deeply embedded core" (DEC) plus "deeply embedded instruction set" (DEIS) for the RISC instruction set, "launch instruction" for JMPAI, "bridge instruction" for the x86 prefix wrapper, "global configuration register" for the Feature Control Register (FCR), and documented the privilege escalation with the name "Rosenbridge".^[11]

See also

• NEC V20/V30, an x86-compatible CPU implementing a similar scheme to enter and exit into an alternate instruction set mode to support Intel 8080 instructions.

Further reading

• US. 20030154359. patent. Apparatus and method for extending a microprocessor instruction set. 2002-05-09. 2003-08-14. 2007-02-20. Centaur Technology. Glenn. Henry. Glenn Henry (IT entrepreneur). Rodney. Hooker. Terry. Parks. "A dual-opcode embodiment provided for by the present invention selects one specific prefix state which indicates that following opcode entities take on an entirely new translation meaning. Such an embodiment is employed in a dual-architecture microprocessor design to execute more than one instruction set. … For example, in an embodiment that increases the number of architectural registers in the microprocessor beyond the number provided for by an existing instruction set architecture will necessarily provide an extended register file … The translation logic also has a micro instruction buffer having an opcode extension field, a micro opcode field, a destination field, a source field, and a displacement field. … In one embodiment, the signal is derived from a feature control register that reads a fuse array that was configured during fabrication of the part..
• US. 20030188130. patent. Mechanism for extending the number of registers in a microprocessor. 2002-05-09. 2003-10-02. 2008-05-13. Centaur Technology. Glenn. Henry. Glenn Henry (IT entrepreneur). Rodney. Hooker. Terry. Parks. The register logic has an extended register file comprising existing architectural registers and additional registers. In an x86 embodiment, registers R0-R7 comprise the eight existing architectural registers and registers R8-R15 comprise eight added registers..
• God Mode unlocked: Hardware backdoors in x86 CPUs. Christopher. Domas. 10 August 2018. DEF CON 26. Las Vegas.
• Book: The Soul of a New Machine. Tracy Kidder. Comments on the use of mode bits in CPUs, in the context of the creation of Data General's Eagle computer.

Notes and References

1. News: VIAs Prozessor der siebten Generation. VIA's seventh-generation processor. 22 January 2003. 12 August 2018. Andreas. Stiller. Heise Online. Heinz Heise. de. Als … kann man Nehemiahs RISC-artigen Core auch native programmieren (AIS: Alternate Instruction Set). Auch hier wird sich zeigen, ob findige Programmierer das für den einen oder anderen Treiber nutzen können, um hier mehr Performance herauszukitzeln..
2. Alternate Instruction Set. 70‒71. VIA Eden. Embedded System Platform Processor Datasheet. 10 August 2018. November 2002.
3. Web site:
   1. 21 add support for Centaur's AIS
   . The Netwide Assembler. 18 December 2002. 12 August 2018. Sourceforge.
4. patent . US . 20080256336 . Microprocessor with private microcode ram . 2007-04-10 . 2008-10-16 . 2010-11-02 . G. Glenn . Henry . Glenn Henry (IT entrepreneur) . Colin . Eddy . Rodney E. . Hooker . Terry . Parks .
5. Web site: Microcode Verification – Another Piece of the Microprocessor Verification Puzzle. Jared. Davis. Anna. Slobodova. Sol. Swords. 20 April 2016. 14 August 2018.
6. VIA, VIA C3 Processor Alternate Instruction Set Programming Reference, version 0.25, november 2002. Accessed on Apr 26, 2023.
7. VIA, VIA C3 Processor Alternate Instruction Set Application Note, version 0.24, 2002. Accessed on Apr 26, 2023.
8. Centaur Extended CPUID Instruction Functions. VIA Eden-N Embedded System Platform Processor Datasheet. Revision 0.92. 22 October 2004. 10 August 2018. 20, 74.
9. Web site: kernlini.c. Microsoft. Microsoft Windows NT kernel source. 14 August 2018. KiGetFeatureBits … // Disable bit 0 which controls the Cyrix ALTINST feature..
10. Alternative Instruction Execution. VIA C3 Samuel 2 Processor Datasheet. October 2004. Version 1.12. 60.
11. Web site: Rosenbridge: Hardware backdoors in x86 CPUs. Christopher. Domas. GitHub. 10 August 2018.
12. News: Hacker Finds Hidden 'God Mode' on Old x86 CPUs. Tom's Hardware. Paul. Wagenseil. 9 August 2018. 10 August 2018.