| ARM Cortex-A78 | |
| Produced-Start: | 2020 |
| Designfirm: | ARM Ltd. |
| Slowest: | 2.4 |
| Fastest: | 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
| Slow-Unit: | GHz |
| L1cache: | 32–64 KB (parity)32kb L1 Instruction cache and 32kb L1 Data cache.or64kb L1 Instruction cache and 64kb L1 Data cache. |
| L2cache: | 256–512 (private L2 ECC) KiB |
| L3cache: | Optional, 512 KB to 4 MB (up to 8 MB) with Cortex-X1 |
| Microarch: | ARM Cortex-A78 |
| Arch: | ARMv8-A |
| Extensions: | ARMv8.1-A, ARMv8.2-A, cryptography, RAS, ARMv8.3-A LDAPR instructions |
| Numcores: | 1–4 per cluster |
| Pcode1: | Hercules |
| Variant: | ARM Cortex-X1 |
| Predecessor: | ARM Cortex-A77 |
| Successor: | ARM Cortex-A710 |
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre.[1]
The ARM Cortex-A78 is the successor to the ARM Cortex-A77. It can be paired with the ARM Cortex-X1 and/or ARM Cortex-A55 CPUs in a DynamIQ configuration to deliver both performance and efficiency. The processor also claims as much as 50% energy savings over its predecessor.
The Cortex-A78 is a 4-wide decode out-of-order superscalar design with a 1.5K macro-OP (MOPs) cache. It can fetch 4 instructions and 6 Mops per cycle, and rename and dispatch 6 Mops, and 12 μops per cycle. The out-of-order window size is 160 entries and the backend has 13 execution ports with a pipeline depth of 14 stages, and the execution latencies consist of 10 stages.
The processor is built on a standard Cortex-A roadmap and offers a 2.1 GHz (5 nm) chipset which makes it better than its predecessor in the following ways:
There is also extended scalability with extra support from Dynamic Shared Unit for DynamIQ on the chipset. A smaller 32 KB L1 cache from the 64 KB L1 cache configuration is optional. To offset this smaller L1 memory, the branch predictor is better at covering irregular search patterns and is capable of following two taken branches per cycle, which results in fewer L1 cache misses and helps hide pipeline bubbles to keep the core well supplied. The pipeline is one cycle longer compared to the A77, which ensures that the A78 hits a clock frequency target of around 3 GHz. The A78 is a 6 instruction per cycle design.
ARM also introduced a second integer multiply unit in the execution unit and an additional load Address Generation Unit (AGU) to increase both the data load and bandwidth by 50%. Other optimizations of the chipset include fused instructions[2] and efficiency improvements to instruction schedulers, register renaming structures, and the re-order buffer.
L2 cache is available up to 512 KB and has double the bandwidth to maximize the performance, while the shared L3 cache is available up to 4 MB, double that of previous generations. A Dynamic Shared Unit (DSU) also allows for an 8 MB configuration with the ARM Cortex-X1.[3] [4] [5] [6]
The Cortex-A78 is available as a SIP core to licensees whilst its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
The Cortex-A78 was first used in Samsung Exynos 2100 SoC, introduced in November and December 2020 respectively.[7] [8] The custom Kryo 680 Gold core used in the Snapdragon 888 SoC is based on the Cortex-A78 microarchitecture.[9] [10] The Cortex-A78 is also used in the MediaTek Dimensity 1200 and 8000 series. The device is also used in NVIDIA DPU, and in the HiSilicon Kirin 9000s, released in August 2023.